Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1999-09-23
2003-03-04
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S400000, C714S814000
Reexamination Certificate
active
06530029
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an I
2
C/SMBus system and, more particularly, to an I
2
C/SMBus start-stop detecting circuit that reduces the likelihood of stalling the bus due to glitches on the data line.
2. Description of the Related Art
In I
2
C and SMBus systems, only two bidirectional lines are used for communication between devices: a serial data line for transferring a data signal, and a serial clock line for transferring a clock signal. (The I
2
C Bus and the SMBus are different busses which, although they are defined by different specifications, follow the same protocol. As a result, each reference to the I
2
C Bus also refers to the SMBus.) During data transfer, the high or low state of the data signal can only change when the clock signal is low.
Within the procedure of the I
2
C bus specification, two unique situations arise which are defined as I
2
C start and I
2
C stop conditions. The I
2
C start condition occurs when the data signal transitions from a high to a low when the clock signal is high, while the I
2
C stop condition occurs when the data signal transitions from a low to a high when the clock signal is high.
Microcontrollers can identify the I
2
C start and I
2
C stop conditions by sampling the data line at least twice per clock period to identify a transition in the data signal, or by using a dedicated I
2
C interface. Slave circuits which do not have access to any faster internal clock signal that could be used to sample the data line, however, must utilize a dedicated I
2
C interface.
Conventionally, a dedicated I
2
C interface identifies the I
2
C start condition by sampling the level of the clock signal when the falling edge of the data signal is detected. However, glitches on the data line during arbitration in a multi-master environment may erroneously invalidate a previously detected I
2
C start condition. Furthermore, glitches on the data line while the I
2
C bus is in an idle state may be erroneously interpreted as an I
2
C start condition. This, in turn, can lead the interface to lock up and stall the bus.
Thus, there is a need for an I
2
C interface which reduces the likelihood that a glitch on the data line invalidates a detected I
2
C start condition or is erroneously detected as an I
2
C start condition.
SUMMARY OF THE INVENTION
By evaluating the start condition twice, the present invention provides an I
2
C start-stop detection circuit that reduces the likelihood that a glitch on the data line invalidates a detected I
2
C start condition or is erroneously detected as an I
2
C start condition.
In accordance with the present invention, a start-stop detection circuit includes a first start detecting circuit that is connectable to a clock line to receive a clock signal, and a data line to receive a data signal. In addition, the detecting circuit is also connected to a first reset line to receive a first reset signal and to a first-step line to output a first-step signal.
The start-stop detection circuit also includes a second start detecting circuit that is connectable to the clock line to receive the clock signal. Further, the second start detecting circuit is also connected to the first-step line to receive the first-step signal, a second reset line to receive a second reset signal, and a start line to output a start signal.
In addition, a reset circuit is connectable to the clock line to receive the clock signal, and a master reset line to receive a master reset signal. The reset circuit is also connected to the start line to receive the start signal, the first reset line to output the first reset signal, and the second reset line to output the second reset signal.
Further, a stop detection circuit is connectable to the clock line to receive the clock signal, the data line to receive the data signal, and the reset line to receive the master reset signal. In addition, the stop detection circuit is also connected to the start line to receive the start signal.
In the present invention, the first start detecting circuit includes an edge detecting circuit and a level detecting circuit. The edge detecting circuit detects a high-to-low voltage transition on the data line, while the level detecting circuit latches and outputs the logic state of the clock signal to form the first-step signal when the edge detecting circuit detects the transition on the data line.
In addition, the second start detecting circuit includes an edge detecting circuit and a level detecting circuit. The edge detecting circuit detects a high-to-low voltage transition on the clock line, while the level detecting circuit latches and outputs the logic state of the first-step signal to form the start signal when the edge detecting circuit of the second start detecting circuit detects the transition on the clock line.
Further, the reset circuit includes a first logic circuit and a second logic circuit. The first logic circuit outputs the first reset signal when the logic state of the master reset signal indicates that a reset has been commanded, or the logic state of the start signal indicates that a valid I
2
C start condition has been detected.
The second logic circuit outputs the second reset signal when the logic state of the master reset signal indicates that a reset has been commanded, or when, on a next rising edge of the clock signal, the logic state of the start signal indicates that a valid start condition has been detected.
In addition, the stop detecting circuit includes an edge detecting circuit and a level detecting circuit. The edge detecting circuit detects a low-to-high voltage transition on the data line, while the level detecting circuit latches and outputs the logic state of the clock signal to form the stop signal when the edge detecting circuit of the stop detecting circuit detects the transition on the data line.
The present invention also includes a method for operating the start-stop detection circuit. The method begins with the step of detecting a high-to-low voltage transition on the data line. The logic state of the clock signal is latched and output to form the first-step signal when the high-to-low transition is detected on the data line.
The method continues with the step of detecting a high-to-low voltage transition on the clock line.
The logic state of the first-step signal is latched and output to form the start signal when the high-to-low transition is detected on the clock line.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 4371975 (1983-02-01), Dugan
patent: 4756006 (1988-07-01), Rickard
patent: 5878234 (1999-03-01), Dutkiewicz et al.
patent: 5925135 (1999-07-01), Trieu et al.
Chang Eric
Lee Thomas
National Semiconductor Corporation
Pickering Mark C.
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