Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt inhibiting or masking
Reexamination Certificate
2008-01-23
2010-12-07
Auve, Glenn A (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt inhibiting or masking
C710S048000, C710S260000
Reexamination Certificate
active
07849246
ABSTRACT:
An I2C bus control circuit includes a continuous transmission control section in addition to a transmission control section, a sequence control section, a data line control section, and a clock line control section. The continuous transmission control section has a number-of-continuous transmission bytes register and first to (n−1)thcontinuous transmission data registers, and supplies an interrupt signal to the controller when continuous transmission is completed or an error is detected. The number of times the controller conducts interrupt processing is thus reduced and the processing time is reduced.
REFERENCES:
patent: 7089338 (2006-08-01), Wooten et al.
patent: 2004/0022204 (2004-02-01), Trembley
patent: 2005/0002384 (2005-01-01), Larson et al.
patent: 2005/0091427 (2005-04-01), Yoshida et al.
patent: 2005/0228915 (2005-10-01), Saripalli et al.
Philips Semiconductors. The 12C-Bus Specification Version 2.1, Jan., 2000, pp. 2-46.
Higuchi Soshi
Konishi Masato
Auve Glenn A
McDermott Will & Emery LLP
Panasonic Corporation
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