I.sup.2 L Ram unit

Details I.sup.2 L Ram unit I.sup.2 L Ram unit

1978-12-04

1980-03-11

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

357 45, 365154, G11C 1140

Patent

active

041931262

ABSTRACT:
The memory unit comprises a plurality of bipolar inverter transistors and an equal number of injector transistors, each of which acts as a current source for a different one of the inverter transistors. Means are provided for cross-coupling a first and a second of the inverter transistors to form a flip-flop. Third, fourth and fifth inverter transistors provide input data flow from the data line to the cross-coupled first and second inverters, in accordance with a write control sixth inverter transistor connected to receive a write signal. A seventh inverter transistor provides data output flow between the cross-coupled first and second inverter transistors and the data line in accordance with the read control eighth inverter transistor connected to receive a read signal.

REFERENCES:
patent: 3177374 (1965-04-01), Simonian

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