I.sup.2 L Memory device

Details I.sup.2 L Memory device I.sup.2 L Memory device

1980-06-03

1982-12-28

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365174, G11C 1140

Patent

active

043665543

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to a semiconductor memory device constituted of a plurality of transistors.


BACKGROUND ART

An IIL logic circuit which requires no separation for each element has recently been used to enhance the integration density of an integrated circuit. Japanese Patent Disclosure No. 49-24329 discloses a semiconductor memory device having a plurality of flip-flop type memory cells constructed with the use of an IIL logic circuit of this type and arranged in a matrix array. In this type of semiconductor memory device, read and write operations are selectively effected through the same address transistor with respect to each memory cell. In this case, a data output signal read out of the memory cell through the address transistor does not have a sufficiently great logic amplitude and in order to positively detect the data output signal a data detection circuit of a complicated structure is needed, making the occupation area of the memory device greater as a whole.
It is accordingly an object of this invention to provide a semiconductor memory device which reads out memory data as a logic signal having a sufficiently great logic amplitude and positively processes data without using a complicated data detection circuit.


DISCLOSURE OF INVENTION

This invention provides a semiconductor memory device having at least one flip-flop type memory cell comprising a first transistor, a second transistor having the same conductivity type as that of the first transistor and having its emitter, collector and base connected to the emitter, base and collector of the first transistor, a third transistor having its base and collector connected to the emitter and collector of the first or the second transistor, and a fourth transistor having its emitter and base connected to the emitter and collector of the second transistor. The memory content of the flip-flop type memory cell is read out by applying readout voltage to the base of the fourth transistor. That is, since with the second transistor ON the collector potential of the second transistor and base potential of the fourth transistor become equal to a reference potential, the fourth transistor is held in a nonconductive state and an output data signal of a first logic level is obtained through an output data line connected to the collector of the fourth transistor. With the second transistor OFF the fourth transistor is rendered conductive and an output data signal of a second logic level is obtained through the output data line. Since in this way the contents of the flip-flop type memory cell is read out according to the ON and OFF states of the fourth transistor the logic amplitude of the output data signal can be made greater. This obviates the need for using a complicated data detection circuit.


BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1 shows a circuit diagram of a semiconductor memory device according to one embodiment of this invention;
FIG. 2 is a plan view showing the semiconductor memory device embodying the circuit of FIG. 1;
FIG. 3 is a cross-sectional view, as taken along line III--III in FIG. 2, showing the semiconductor memory device of FIG. 2;
FIG. 4 is a block diagram showing a semiconductor memory device including a plurality of flip-flop type memory cells arranged in a matrix array;
FIGS. 5 and 6 are a circuit diagram and plan view, respectively, showing another embodiment of this invention;
FIG. 7 shows a semiconductor memory circuit according to another embodiment of this invention;
FIGS. 8 and 9 are a circuit diagram and plan view, respectively, showing a semiconductor memory device according to another embodiment of this invention;
FIG. 10 shows a modified form of semiconductor memory device of FIG. 2;
FIG. 11 shows a modified form of semiconductor memory device shown in FIG. 1; and
FIG. 12 shows a modified form of semiconductor memory device shown in FIG. 1.


BEST MODE OF CARRYING OUT THE INVENTION

A semiconductor memory circuit according to one embodiment of this invention includes, as shown in FIG. 1, an NPN tr

REFERENCES:
patent: 3986178 (1976-10-01), McElroy et al.
patent: 4081697 (1978-03-01), Nakano
patent: 4228525 (1980-10-01), Kawarada et al.

Affiliated with

Also associated with

Rating

I.sup.2 L Memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with I.sup.2 L Memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and I.sup.2 L Memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1340842