I.sub.DDQ -testable RAM

Details I.sub.DDQ -testable RAM I.sub.DDQ -testable RAM

1994-08-31

1996-02-13

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

36518901, G11C 1300

Patent

active

054916658

ABSTRACT:
An electronic circuit includes an array of a number of memory cells that are functionally organized in rows and columns. The circuit includes test circuitry that is selectively operative to access all cells of the array in parallel. An I.sub.DDQ -test then discovers whether or not there is a defect in any of the cells. This results in a test circuit which is faster, more efficient and more economical than previously-available circuits.

REFERENCES:
patent: 5351213 (1994-09-01), Nakashima
patent: 5400281 (1995-03-01), Morigami
"A Current Testing for CMOS Static RAMs", By Hiroshi Yokoyama et al, Department of Information Engineering, Akita University, Akita City, Akita 010 Japan, 1993 IEEE.
"A New Testing Acceleration Chip for Low-Cost Memory Tests" M. Inoue et al IEEE Design & Test of Computers, Mar. 1993, pp. 15-19.
Intel Memory Products Data Handbook, 1992, pp. 3-320-3-323.

Affiliated with

Also associated with

Rating

I.sub.DDQ -testable RAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with I.sub.DDQ -testable RAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and I.sub.DDQ -testable RAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-244735