Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2006-10-26
2009-12-22
Lane, Jack A (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
07636832
ABSTRACT:
Methods and apparatus to provide improved input/output (I/O) address translation lookaside buffer performance are described. In one embodiment, one or more entries of a cache (e.g., an I/O address translation lookaside buffer) are locked in response to a request to lock the one or more entries. Other embodiments are also described.
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Raj Ashok
Shah Rajesh
Caven & Aghevli LLC
Intel Corporation
Lane Jack A
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