I/O pin placement for a programmable logic device

Details I/O pin placement for a programmable logic device I/O pin placement for a programmable logic device

2006-09-19

2006-09-19

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07111265

ABSTRACT:
A method and associated computer program product is provided for determining placement of I/O pins on an integrated circuit device. In an exemplary embodiment, a set of pins to be placed is partitioned into pin groups prior to placing individual pins. After partitioning the pins into pin groups, pin groups may, in a preferred embodiment, be ranked according to difficulty of placement. Pins in the most difficult group are placed first by applying a method that, in a preferred embodiment, places pins within the limits imposed by current density requirements while achieving high pin density within those limits when pad resources are relatively limited.

REFERENCES:
patent: 6289496 (2001-09-01), Anderson et al.
“Using Selectable I/O Standards in Stratix Devices”, Altera Corp., Application Note 201, ver. 1.0, Feb. 2002, pp. 1-36.
“Using High-Speed Differential I/O Interfaces in Stratix Devices”, Altera Corp., Application Note 202, ver. 1.2, May 2002, pp. 1-11.
“Stratix Programmable Logic Device Family Data Sheet”, Preliminary Info., Altera Corp. 2002, pp. 123-132.
“Using the Virtex Select I/O Resource”, XILINX Inc., Application Note: Virtex Series, XAPP133 (v2.5) Sep. 7, 2000, pp. 1-10.
Altera Device Data Book, Altera Corp., May 2999, title page, copyright page, pp. 66, 67.
“XC4000XLA/XV Field Programmable Gate Arrays”, Product Specification, XILINX Inc., vl.3 Oct. 18, 1999.
J. Anderson, et al., “A Placement Algorithm for FPGA Designs with Multiple I/O Standards”, XILINX Inc., FPGA Symposium 2001, pp. 1-14.

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