Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2004-12-29
2009-08-25
Tsai, Henry W. H. (Department: 2184)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C711S141000, C711S142000
Reexamination Certificate
active
07581042
ABSTRACT:
The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.
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Crossland James B.
Cummings Greg
Minturn Dave
Sen Sujoy
Intel Corporation
Mamo Elias
McAbee David P.
Tsai Henry W. H.
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