I/O driver power distribution method for reducing silicon area

Details I/O driver power distribution method for reducing silicon area I/O driver power distribution method for reducing silicon area

2005-10-20

2008-10-07

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07434189

ABSTRACT:
Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC includes a long distance power and ground distribution network, an input output (IO) power and ground distribution network, a number of macro processing circuits, and IO circuits. The long distance power and ground distribution network electrically couples to the IO power and ground distribution network. Both the power and ground distribution networks may be located within the upper level conductive layers. IO power and ground distribution network locally supplies power and ground to IO circuits. Macro processing circuits may be located beneath the power distribution network as some macro processing circuits do not require access to upper level conductive layers. By placing these macro processing circuits beneath these power distribution networks, die size may be reduced.

REFERENCES:
patent: 6925627 (2005-08-01), Longway et al.
patent: 2001/0049813 (2001-12-01), Chan et al.
patent: 2005/0091629 (2005-04-01), Eisenstadt et al.

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