I/O device layout during integrated circuit design

Details I/O device layout during integrated circuit design I/O device layout during integrated circuit design

2000-01-26

2002-09-24

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C438S014000

Reexamination Certificate

active

06457157

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention.
The present invention generally relates to the art of microelectronic integrated circuit design, and particularly relates to layout of input/output devices on an integrated circuit die.
2. Description of the Related Art.
FIG. 1
provides a representational illustration of a typical integrated circuit (IC) chip (or die)
10
which includes a semiconductor substrate
12
, upon which are formed the electronic devices used to implement the chip's functionality. The logic circuitry of the integrated circuit is formed on the interior portion
20
of the semiconductor substrate
12
. The logic portion includes a number of functional circuit blocks that can have different sizes and shapes. The larger blocks can include, for example, central processing units such as CPU
21
, read-only memories such as ROM
22
, clock/timing units such as clock/timing unit
23
, random access memories such as RAMs
24
, and I/O units such as I/O unit
25
for providing an interface between CPU
21
and peripheral devices. These blocks, commonly known as macroblocks, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries. The logic portion further includes tens of thousands, hundreds of thousands or even millions or additional small cells
26
. Each cell
26
represents a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries.
Along the periphery of the semiconductor substrate are various input, output or combined input and output (input/output or I/O) devices or cells
16
., In a wire-bond IC chip, each such I/O device generally has connected to it at least one metal bonding pad
18
which is used as an electrical connection for an input/output signal. The wire-bond IC die is then mounted within a plastic or ceramic package having multiple pins, and wire connections are made between the die's bonding pads and the package's pins. Finally, the package containing the IC die is mounted onto a printed circuit board in a manner so as to form electrical connections between the pins of the IC and other components on the printed circuit board. In this manner, external signals can be provided to and from the IC die.
Certain of pads
18
are connected to external power (VDD) and ground (VSS). Each such pad is connected to a power I/O cell, which in turn is connected to one of the chip's power and ground rings, respectively. More specifically, power ring
30
and ground ring
31
supply power and ground to the I/O circuitry. Similarly, power ring
32
and ground ring
33
provide power and ground to the internal logic circuitry
20
. In order to isolate the internal logic power circuit from the I/O power circuit, certain pad and power I/O cell combinations are connected only to the internal logic power/ground rings, and separate pad and power I/O cell combinations are connected only to the I/O circuit power/ground rings. To further isolate the power/ground supplies for certain sensitive circuits from the power/ground supplies for noisier circuits, cuts are made in the rings (not shown). Each resulting ring segment can then be used to supply a different type of circuit. Also, although only a single I/O power ring is shown, mixed-voltage integrated circuits may utilize a different power ring for each different voltage.
During the physical design stage of conventional IC design, I/O devices.
16
, internal logic blocks
21
-
24
and internal logic cells
26
typically are laid out on the semiconductor substrate in such a manner as to make the most efficient use of the available die space, as well as to permit the routing of required connections between the various devices. However, upon completion of physical design and implementation of design rule checking, it was sometimes discovered that the design was not feasible for actual implementation because one or more bonding pads
18
had been placed too close to either neighboring pads or neighboring pad wires (i.e., the wire connecting an I/O device and its pad). In particular, it often was discovered that, due to fabrication limitations, fabrication of the integrated circuit was likely to result in unwanted short circuits. Upon discovering such problems, it was then necessary to go back and revise the physical design, often at significant expense and delay, in order to attempt to eliminate the problem.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing situation by imposing minimum pad spacing criteria for the layout of I/O devices and pads.
According to one aspect, the invention lays out input/output (I/O) pairs, each including an I/O cell and a pad, on an integrated circuit die. Size information is obtained for each of a first I/O pair and a second I/O pair. A minimum pad spacing criterion is obtained which specifies a minimum distance between the pad in the first I/O pair and an element of the second I/O pair, and the first I/O pair and the second I/O pair are laid out so as to satisfy the minimum pad spacing criterion.
According to a further aspect, the invention lays out input/output (I/O) pairs, each including an I/O cell and a pad, on an integrated circuit die. Size information is obtained for each of the I/O pairs. Minimum pad spacing criteria are obtained, including a required minimum center-to-center spacing between two pads in a same row and a required minimum distance between closest edges of two pads in a same row. Each of the I/O pairs are then laid out so as to satisfy the minimum pad spacing criteria
According to a still further aspect, the invention lays out pads for input/output cells on an integrated circuit die. Size information is obtained for each of a first I/O cell pad and a second I/O cell pad. A minimum pad spacing criterion is obtained, and the first I/O cell pad and the second I/O cell pad are laid out so as to satisfy the minimum pad spacing criterion.
By virtue of the foregoing arrangements, the present invention frequently can avoid fabrication problems that might result in undesirable short circuits and that might not otherwise be discovered until later in the design process. As a result, the invention can often avoid the cost and delay of having to perform physical redesigns.
According to more particularized aspects of the invention, pads are staggered in at least two different rows, and the minimum pad spacing criteria also include a required minimum distance between the closest edges of the current pad and the wire corresponding to the a next subsequent pad in a higher row than that of the current pad. This aspect of the invention often can provide additional protection against fabrication problems.


REFERENCES:
patent: 4745305 (1988-05-01), Crafts
patent: 5155065 (1992-10-01), Schweiss
patent: 5552333 (1996-09-01), Cheung et al.
patent: 5581109 (1996-12-01), Hayashi et al.
patent: 5777354 (1998-07-01), Cheung et al.
patent: 6127208 (2000-10-01), Amiya et al.
patent: 6130550 (2000-10-01), Zaliznyak et al.
Caldwell et al, “Implications of Area-Array I/O For-Based Placement Methodology,” IEEE, Feb. 1998, pp. 1-7.

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