Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-28
2001-02-06
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S357000, C257S363000, C438S199000, C438S210000
Reexamination Certificate
active
06184557
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to input/output (I/O) circuits and, more particularly, to an I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event, and as diodes for electrostatic discharge (ESD) protection.
2. Description of the Related Art
In recent years, increasing attention has been devoted to protecting packaged integrated circuits from damage that results from an electrostatic discharge (ESD) event. This has become more important as the gate oxide thicknesses of MOS transistors have become thinner due to the improved processing technologies that are now commonly in use.
An ESD event typically occurs when the packaged chip is exposed to static electricity, such as when the pins are touched by an ungrounded person handling the chip prior to installation, or when the chip slides across another surface on its pins.
FIG. 1
shows a schematic and cross-sectional drawing that illustrates a conventional input/output (I/O) circuit
100
. As shown in
FIG. 1
, circuit
100
includes an I/O pad
110
which is connected to an I/O pin (not shown), and a driver circuit
112
which is connected to pad
110
.
As further shown in
FIG. 1
, driver circuit
112
includes a n-channel transistor
114
which is formed in a p− substrate
116
, and a p-channel transistor
118
which is formed in a n− well
120
which, in turn, is formed in substrate
116
.
N-channel transistor
114
has spaced-apart source and drain regions
122
and
124
which are formed in substrate
116
, and a channel region
126
which is defined between source and drain regions
122
and
124
. Source and drain regions
122
and
124
each include a n+diffusion region
130
and a layer of silicide
132
which is formed over diffusion region
130
.
In addition to the above, transistor
114
also has a layer of gate oxide
134
which is formed over channel region
126
, and a gate
136
which is formed on gate oxide layer
134
over channel region
126
.
Similarly, p-channel transistor
118
has spaced-apart source and drain regions
142
and
144
which are formed in well
120
, and a channel region
146
which is defined between source and drain regions
142
and
144
. Source and drain regions
142
and
144
each include a p+diffusion region
150
and a layer of silicide
152
which is formed over diffusion region
150
.
As with transistor
114
, transistor
118
also has a layer of gate oxide
154
which is formed over channel region
146
, and a gate
156
which is formed on gate oxide layer
154
over channel region
146
.
As additionally shown in
FIG. 1
, I/O circuit
100
further includes a first pair of electrostatic discharge (ESD) protection diodes D
1
and D
2
, and a resistor R
1
which are each connected to pad
110
. Diode D
1
has an input connected to pad
110
, and an output connected to a supply rail
164
, while diode D
2
has an input connected to ground and an output connected to pad
110
.
Further, circuit
100
also includes a second pair of ESD protection diodes D
3
and D
4
, and an internal circuit
162
which are each connected to resistor R
1
. Diode D
3
has an input connected to resistor R
1
and internal circuit
162
, and an output connected to supply rail
164
. Diode D
4
has an input connected to ground, and an output connected to resistor R
1
and internal circuit
162
.
In operation, when the voltage on pad
110
rises above a supply voltage VDD on supply rail
164
due to an ESD event, ESD protection diodes D
1
and D
3
become forward biased and turn on to “sink” the ESD voltage on pad
110
to supply rail
164
. Similarly, when an ESD voltage on pad
110
falls below ground, diodes D
2
and D
4
become forward biased and turn on to “short”pad
110
to ground.
One drawback of I/O circuit
100
is that since drain regions
124
and
144
of transistors
114
and
118
are connected to I/O pad
110
, the large positive and negative ESD voltages that appear on pad
110
also appear on drain regions
124
and
144
. These large ESD voltages on drain regions
124
and
144
, however, can break down gate oxide layers
134
and
154
before diodes D
1
-D
4
have had a chance to fully dissipate the event.
This breakdown, which is only exacerbated by the presence of highly conductive silicide layers
132
and
152
(which are both typically formed during the same processing step), damages or destroys the driver transistors.
One approach for reducing the voltage that appears on drain regions
124
and
144
during an ESD event is to resistively delay the ESD voltage from reaching drain regions
124
and
144
, thereby providing diodes D
1
-D
4
with additional time to dissipate the event.
FIG. 2
shows a schematic and cross-sectional drawing that illustrates a first-type of a conventional resistively-delayed input/output (I/O) circuit
200
. Circuit
200
is similar to circuit
100
and, as a result, utilizes the same reference numerals to represents the structures which are common to both circuits.
As shown in
FIG. 2
, circuit
200
differs from circuit
100
in that circuit
200
includes a thin-film resistor R
2
which is connected between pad
110
and drains
124
and
144
. Although resistor R
2
resistively delays an ESD event from reaching drain regions
124
and
144
, thin-film resistors occupy a significant amount of silicon real estate and require additional fabrication steps.
Rather than using thin-film resistors, diffused substrate regions may also be used as resistors.
FIG. 3
shows a schematic and cross-sectional drawing that illustrates a second-type of a conventional resistively-delayed input/output (I/O) circuit
300
. Circuit
300
is similar to circuit
100
and, as a result, utilizes the same reference numerals to represents the structures which are common to both circuits.
As shown in
FIG. 3
, circuit
300
differs from circuit
100
in that circuit
300
includes a pair of diffused substrate regions RN and RP. Region RN includes a n− well
310
which is formed in p-substrate
116
, and a pair of spaced-apart n+ contacts
312
and
314
which are formed in n− well
310
. Contact
312
is connected to pad
110
, while contact
314
is connected to drain region
124
.
Region RP includes an n− well
320
which is formed in p− substrate
116
, and a p+ region
322
which is formed in the surface of n− well
320
. P+ region
322
is relatively shallow as p+ region
322
is formed during the same step that forms the source and drain regions of p-channel transistor
118
and the p-channel CMOS transistors of the internal circuitry. As shown, one end of p+ region
322
is connected to pad
110
, while the other end of p+ region
322
is connected to drain region
144
.
In operation, regions RN and RP resistively delay an ESD event from reaching drain regions
124
and
144
, thereby providing diodes D
1
-D
4
additional time to dissipate the ESD event.
One problem with circuit
300
, however, is that it is difficult, if not impossible, to obtain a symmetric output from driver transistors
114
and
118
. N− well
310
has a sheet resistance of approximately 1.0-1.5 K&OHgr;/square, while p+ region
322
of n− well
320
has a sheet resistance of approximately 40-150&OHgr;/square.
Thus, to balance the resistances provided by regions RN and RP, p+ region
322
and, therefore, n− well
320
, must be approximately 10× longer than n− well
310
. Being 10× longer, however, substantially increases the capacitance of p+ region
322
which, in turn, prevents driver transistors
114
and
118
from having symmetric outputs.
Thus, there is a need for an I/O circuit that can resistively delay an ESD event from reaching the drain regions of the driver transistors, and provide more symmetric outputs.
SUMMARY OF THE INVENTION
Conventionally, when a pair of diffused substrate regions with opposing conductivity types are utilized to resistively delay an electrostatic discharg
Bergemont Albert
Kalnitsky Alexander
Lin Hengyang (James)
Poplevine Pavel
Crane Sara
Limbach & Limbach L.L.P.
National Semiconductor Corporation
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