I/O bias circuit insensitive to inadvertent power supply variati

Details I/O bias circuit insensitive to inadvertent power supply variati I/O bias circuit insensitive to inadvertent power supply variati

1996-10-18

1998-09-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365208, G11C 702

Patent

active

058124748

ABSTRACT:
An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off. During this period, the biasing circuit interacts with the memory cell to bias the first node to a potential corresponding to the state of the memory cell. Also during the second period of time the sense amplifier is enabled to detect the state of the memory cell by sensing the potential on the first node.

REFERENCES:
patent: 4271487 (1981-06-01), Craycraft et al.
patent: 4932002 (1990-06-01), Houston
patent: 5023841 (1991-06-01), Akrout et al.
patent: 5434821 (1995-07-01), Watanabe et al.
patent: 5526314 (1996-06-01), Kumar

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