Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2002-11-26
2004-04-13
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S305000, C712S011000, C716S030000
Reexamination Certificate
active
06721830
ABSTRACT:
BACKGROUND INFORMATION
DFP-Based Systems
German Patent No. DE 44 16 881 describes data flow processors (DFPs) in which lines of each edge cell, i.e., a cell at the edge of a cell array often in direct contact with the terminals of the unit, lead outward via the terminals of the unit. The lines do not have any specific function. Instead, the lines assume the function that is written into the edge cells. Several DFPs may be interconnected to form a matrix by connecting all terminals.
Systems with Two- or Multi-Dimensional Programmable Cell Architectures
In systems with two- or multi-dimensional programmable cell architectures, such as field programmable gate arrays (FPGAs) and dynamically programmable gate arrays (DPGAs), a certain subset of internal bus systems and lines of the edge cells are connected to the outside via the unit terminals. The lines do not have any specific function, and instead they assume the function written in the edge cells. If several FPGAs/DPGAs are interconnected, the terminals assume the function implemented in the hardware or software.
PROBLEMS
DFP-Based Systems
The wiring complexity for peripherals or for interconnecting DFPs is very high, because the programmer must also ensure that the respective functions are integrated into the cells of the DFP(s). For connecting a memory, a memory management unit must be integrated into the unit. For connecting peripherals, the peripherals must be supported. Additionally, cascading of DFPs must be similarly taken into account. This is relatively complicated. Moreover, space in the unit is lost for the respective implementations.
Systems with Two- or Multi-Dimensional Programmable Cell Architectures (FPGAs, DPGAs)
The above also applies to FPGAs and DPGAs, in particular when the FPGAs and DPGAs implement algorithms or operate as arithmetic (co)processors.
SUMMARY
In accordance with an example embodiment of the present invention, the expense of wiring, in particular the number of unit terminals required, is greatly reduced. A uniform bus system operates without any special consideration by a programmer. A permanent implementation of the bus system control is provided. Memory and peripherals can be connected to the bus system without any special measures. Likewise, units can be cascaded with the help of the bus system.
According to the present invention, a general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memory devices, peripherals or other units (i.e., cascading) can be connected to the bus system.
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Münch Robert
Vorbach Martin
PACT XPP Technologies AG
Ray Gopal C.
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