Patent
1975-12-24
1977-10-18
Larkins, William D.
357 35, 357 36, 357 44, 357 50, 357 89, H01L 2972, H01L 2704, H03K 1908
Patent
active
040549003
ABSTRACT:
An integrated injection logic semiconductor device which comprises an N type semiconductor substrate; a P type semiconductor layer superposed on the N type semiconductor substrate; a first N type region formed in the P type semiconductor layer; a second N type region formed in the P type semiconductor layer; and a P type region formed in the first N type region, wherein the first N type region is connected to the N type semiconductor substrate through an N type connector region formed between the first N type region and N type semiconductor substrate.
REFERENCES:
patent: 3736477 (1973-05-01), Berger et al.
patent: 3947865 (1976-03-01), Russell
patent: 3982266 (1976-09-01), Matzen et al.
Ito Shintaro
Nakai Masanori
Nakamura Jun-ichi
Nishi Yoshio
Shinozaki Satoshi
Larkins William D.
Tokyo Shibaura Electric Co. Ltd.
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