Hysteresis input buffer

Details Hysteresis input buffer Hysteresis input buffer

1998-09-24

2001-02-13

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S086000, C326S087000, C326S023000, C326S024000, C326S112000, C326S119000, C326S121000, C327S205000, C327S206000

Reexamination Certificate

active

06188244

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a hysteresis input buffer and, more particularly, to a hysteresis input buffer for providing an adequate noise margin and a high speed response depending on the characteristics of an input signal.
2. Discussion of Related Art
Conventional input buffers are used in semiconductor integrated circuits to control the transfer time or voltage level of input signals externally received from an outside source. The conventional input buffers transform the TTL (Transistor Transistor Logic) levels of the input signals into CMOS (Complementary Metal-Oxide Semiconductor) levels for use in the integrated circuits.
The conventional input buffers are generally constructed by inverters connected in multistages, and especially by CMOS inverters each formed with a PMOS transistor and an NMOS transistor connected in series between a supply voltage terminal and the ground. If there is an even number of CMOS inverters connected in series (forming an even number of stages), it is possible to transform the voltage level of the input signals to a desired level without inverting the input signals, depending on the driving capabilities of the CMOS inverters. If an odd number of the CMOS inverters are connected in series (forming an odd number of stages), the input signals are inverted by the CMOS inverters.
Although the conventional input buffers can be structured in many different ways, two buffer types—inverter type CMOS input buffers and hysteresis input buffers—are generally used. The inverter type CMOS input buffers are CMOS input buffers connected in two stages and the hysteresis input buffers are inverter type CMOS input buffers manifesting hysteresis characteristics.
FIGS.
1
(
a
) and
2
(
a
) show examples of the inverter type CMOS input buffer and the hysteresis input buffer, respectively. FIG.
1
(
a
) shows a circuit of a conventional inverter type CMOS input buffer and FIG.
1
(
b
) shows a characteristic curve of the input/output of the buffer of FIG.
1
(
a
).
As shown in FIG.
1
(
a
), the inverter type CMOS input buffer includes first and second CMOS inverters INV
1
and INV
2
. These inverters INV
1
and INV
2
are connected in series to each other wherein the inverter INV
1
represents the input stage of the buffer and the inverter INV
2
represents the output stage of the buffer. The CMOS inverter INV
1
includes a PMOS transistor Q
1
and an NMOS transistor Q
2
connected in series with their drains connected to an output node N
1
. A supply voltage VDD terminal is coupled to the source of the PMOS transistor Q
1
, and the source of the NMOS transistor Q
2
is grounded by the ground voltage VSS terminal. Although not shown in the drawings, the CMOS inverter INV
2
has the same configuration as the inverter INV
1
.
When an input signal IN transiting from a high level to a low level is input to the buffer, the PMOS transistor Q
1
is turned on and a current path is established between the supply voltage VDD terminal and the output node N
1
. The current supplied by the supply voltage VDD raises the voltage of the output node N
1
and the voltage at the node N
1
is inverted by the inverter INV
2
. With a low level input signal IN, the buffer generates a low level output signal OUT.
When the input signal IN transits from a low level to a high level, the PMOS transistor Q
1
is turned off, the NMOS transistor Q
2
is turned on, and a current path is established between the output node N
1
and the ground terminal. Current flows to the ground terminal and decreases the voltage VN
1
at the output node N
1
. At this time the input signal IN is in a high level and the voltage VN
1
is in a low level. The low level node voltage VN
1
is inverted by the inverter INV
2
. As a result, with a high level input signal IN, the buffer generates a high level output signal OUT. The input signal IN and the output signal OUT of the conventional buffer in FIG.
1
(
a
) then have the same voltage levels at a given time.
Depending on the threshold levels of the CMOS transistors used in the conventional input buffer, the logical value of the input signal changes. Parameters for setting the threshold levels of conventional CMOS transistors include a high level input voltage VIH and a low level input voltage VIL. The high level input voltage VIH is defined to be the minimum value of a voltage range recognized by a CMOS inverter as the high level. The low level input voltage VIL is defined to be the maximum value of a voltage range recognized by a CMOS inverter as the low level.
In the input/output characteristic curve shown in FIG.
1
(
b
), the high level input voltage VIH and the low level input voltage VIL for the conventional buffer as shown in FIG.
1
(
a
) are located where the input voltage VIN has the unity gain of one (1). The input voltage VIN is the voltage of the input signal IN.
A further discussion on the operation of the conventional CMOS inverter INV
1
in accordance with the parameters VIH and VIL is as follows.
When the level of the input voltage VIN is between the low level input voltage VIL and the ground voltage, the node voltage VN
1
becomes high and is input to the CMOS inverter INV
2
. When the level of the input voltage VIN is between the high level input voltage VIH and the supply voltage VDD, the voltage VN
1
becomes low and is input to the inverter INV
2
. The inverter IN
2
inverts the voltage VN
1
to generate the output signal OUT.
By properly setting the values of the low and high level input voltages VIL and VIH in both CMOS inverters INV
1
and INV
2
, the output voltage range of the CMOS inverter INV
1
can be modified in accordance with the voltage range allowed by the CMOS inverter INV
2
. However, if noise is provided to these CMOS inverters so that the input voltage level VIN fluctuates, the voltage VIN also fluctuates and an unstable output signal OUT is generated from the CMOS inverter INV
2
. For example, if the input voltage VIN is slightly lower than or equal to the low level input voltage VIL and noise is mixed into the voltage VIN to momentarily increase the voltage VIN to a level higher than the voltage VIL, an undesired low level (instead of a high level) voltage VN
1
and a high level output signal OUT will be generated. That is, with a low level input voltage VIN, a high level output signal OUT is generated which is contrary to the expected output level. Therefore, the conventional inverter type CMOS input buffer as described above has a problem of instability for use in integrated circuits (ICs) which require extremely high reliability.
In order to solve this problem of noise in the conventional inverter type CMOS input buffer, an input buffer having hysteresis characteristics is used. FIG.
2
(
a
) shows a circuit of a conventional hysteresis input buffer and FIG.
2
(
b
) shows hysteresis curves for the input/output of the buffer shown in FIG.
2
(
a
).
As shown in FIG.
2
(
a
), a conventional hysteresis input buffer includes a CMOS inverter INV
3
at the input stage and a CMOS inverter INV
4
at the output stage. The CMOS inverter INV
3
includes a PMOS transistor Q
3
and an NMOS transistor Q
4
connected to each other in series wherein the supply voltage VDD is applied to the PMOS transistor Q
3
and the NMOS transistor Q
4
is connected to the ground voltage VSS. The CMOS inverter INV
3
also includes a PMOS transistor Q
5
and an NMOS transistor Q
6
which are connected to each other in series, similar to the structure of PMOS and NMOS transistors Q
3
and Q
4
. The transistors Q
3
and Q
4
are connected in parallel with the transistors Q
5
and Q
6
between the supply voltage VDD terminal and the ground voltage VSS terminal. All the drains of the transistors Q
3
-Q
6
are connected together at an output node N
2
.
The gates of the PMOS and NMOS transistors Q
3
and Q
4
are controlled by the input signal IN and the gates of the PMOS and NMOS transistors Q
5
and Q
6
are controlled by the output signal OUT of the CMOS inverter INV
4
. In other words, the hysteresis

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