Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-10-03
2006-10-03
Elmore, Reba I. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S156000, C710S112000
Reexamination Certificate
active
07117308
ABSTRACT:
A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus. To that end, each device is configured to manage its own set of buffer descriptors, unlike previous data path protocols in which only one device managed all the buffer descriptors. As such, neither device has to perform a read transaction to retrieve a “free” buffer descriptor from the other device. As a result, only write transactions are performed for transferring descriptors across the HPT bus, thereby decreasing the amount of traffic over the bus and eliminating conventional latencies associated with read transactions. In addition, because descriptors are separately managed in each device, the data path protocol also conserves processing bandwidth that is traditionally consumed by managing ownership of the buffer descriptors within a single device.
REFERENCES:
patent: 6757768 (2004-06-01), Potter et al.
patent: 6832279 (2004-12-01), Potter et al.
patent: 2005/0213570 (2005-09-01), Stacy et al.
HyperTransport Technology Consortium, HyperTransport I/O Link Specification, Rev. 1.10, Aug. 25, 2003.
Barach David Richard
Hoult Kent
Mitten John W.
Potter, Jr. Kenneth H.
Riedle Christopher G.
Cesari and McKenna LLP
Cisco Technology Inc.
Elmore Reba I.
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