Hyper page mode control circuit for a semiconductor memory devic

Details Hyper page mode control circuit for a semiconductor memory devic Hyper page mode control circuit for a semiconductor memory devic

1996-11-27

1998-11-10

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Byte or page addressing

365203, 36518911, G11C 700

Patent

active

058354492

ABSTRACT:
An output control circuit for a semiconductor memory device allows the output data to be controlled by a write enable line and/or an output enable line in hyper page mode. An output write enable control signal is generated in response to a column address strobe signal, an output enable signal and a write enable signal. A precharge signal is generated in response to the output write enable control signal, thereby allowing a data bus line to be precharged in hyper page mode. The output enable signal and the write enable signal can be selectively coupled to an output write enable control signal generating circuit to allow the output control circuit to operate in different modes. A trigger signal, which controls a data output buffer and driver circuit, is controlled in response to a latch signal. The latch signal is generated by latching the write enable signal in response to the column address strobe signal. The output control circuit allows the data bus line to be precharged between consecutive bits of output data in hyper page mode.

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