Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-22
2002-04-16
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S649000, C438S651000, C438S655000, C438S664000, C438S299000
Reexamination Certificate
active
06372644
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the fabrication of semiconductor devices, particularly to self-aligned silicide (salicide) technology. The present invention is particularly applicable to ultra large scale integrated circuit (ULSI) systems having features in the deep sub-micron regime.
BACKGROUND ART
As integrated circuit geometries continue to plunge into the deep sub-micron regime, it becomes increasingly more difficult to accurately form discreet devices on a semiconductor substrate with the requisite reliability. High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the R×C product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, continuing reduction in design rules into the deep sub-micron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
A common approach to reduce the resistivity of the interconnect to less than that exhibited by polysilicon alone, e.g., less than about 15-300 ohm/sq, comprises forming a multilayer structure consisting of a low resistance material, e.g., a refractory metal silicide, on a doped polycrystalline silicon layer, typically referred to as a polycide. Advantageously, the polycide gate/interconnect structure preserves the known work function of polycrystalline silicon and the highly reliable polycrystalline silicon/silicon oxide interface, since polycrystalline silicon is directly on the gate oxide.
Various metal silicide have been employed in salicide technology, such as titanium, tungsten, and cobalt. Nickel, however, offers particularly advantages, vis-à-vis other metals in salicide technology. Nickel requires a lower thermal budget in that nickel silicide can be formed in a single heating step at a relatively low temperature of about 250° C. to about 600° C. with an attendant reduction in consumption of silicon in the substrate, thereby enabling the formation of ultra-shallow source/drain junctions.
In conventional salicide technology, sputter etching is typically conducted to remove a thin native oxide layer, e.g., about 10 Å to about 15 Å, on the silicon surfaces prior to depositing a layer of the metal on the gate electrode and on the exposed surfaces of the source/drain regions. Heating is then conducted to form the metal silicide. Unreacted metal is then removed from the dielectric sidewall spacers leaving metal silicide contacts or the upper surface of the gate electrode and on the source/drain regions. In implementing salicide technology, it was found advantageous to employ silicon nitride sidewall spacers, since silicon nitride is highly conformal and enhances device performance, particularly for p-type transistors. However, although silicon nitride spacers are advantageous from such processing standpoints, it was found extremely difficult to effect nickel silicidation of the gate electrode and source/drain regions without undesirable nickel silicide bridging therebetween along the surface of the silicon nitride sidewall spacers, thereby causing short circuiting.
Accordingly, there exists a need for salicide methodology enabling the implementation of nickel silicide interconnection systems without bridging between the nickel silicide layers on the gate electrode and the source/drain regions.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device having nickel silicide contacts on a gate electrode and associated source/drain regions without bridging therebetween along insulative sidewall spacers, notably silicon nitride sidewall spacers.
Additional advantages and other features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned by practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a silicon gate electrode having opposing side surfaces on a silicon substrate with a gate insulating layer therebetween; forming silicon nitride sidewall spacers on the opposing side surfaces of the gate electrode leaving exposed adjacent surfaces of the substrate; treating the silicon nitride sidewall spacers to form hydrogen passivated surfaces; depositing a layer of nickel on the gate electrode and on the exposed substrate surfaces; and heating to react the layer of nickel with underlying silicon to form a layer of nickel silicide on the gate electrode and layers of nickel silicide on the exposed surfaces of the substrate.
Embodiments of the present invention include treating the nickel silicide spacers with a solution of hydrofluoric acid (HF) and water (H
2
O), as at a HF:H
2
O volume ratio of about 100:1 to about 200:1 for up to about 60 seconds to form the hydrogen passivated surfaces, thereby substantially reducing or preventing bridging along the silicon nitride spacers.
Additional advantages of the present invention will become readily apparent to those having ordinary skill in the art from the following detailed description, wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated of carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illutstrative in nature, and not as restrictive.
REFERENCES:
patent: 6156654 (2000-12-01), Ho et al.
patent: 6225197 (2001-05-01), Maekawa
Xiang et al, “Deep Sub-100nm CMOS with Ultra Low Gate Sheet Reistance by NiSi”, VLSI Technology 2000, Digest of Technical Paper Symposium, Jun. 13, 2000, pp 76-77.*
Poon et al, “Thermal Stability of Nickel Silicide Films in Submicron p-type Polysilicon lines”, Electronic Devices Meetings 1997, Proceeding, Aug. 30, 1997, pp 54-58.
Foster John C.
King Paul L.
Nguyen Tuan H.
Pham Thanhha
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