Hybrid tag architecture for a cache memory

Details Hybrid tag architecture for a cache memory Hybrid tag architecture for a cache memory

1997-08-11

1999-12-07

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711143, G06F 1208

Patent

active

060000171

ABSTRACT:
A cache memory system having a hybrid tag architecture and a series of data lines is disclosed. The cache memory includes a cache controller and a dirty tag memory included within the cache controller. The dirty tag memory indicates the status of each data line in the cache memory. A tag memory is coupled to the cache controller and is located external to the cache controller.

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