Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-09-25
2001-06-12
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06246093
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to MOSFET devices and more particularly to a hybrid buried-channel MOSFET device capable of increased drive current without changing the drawn gate length.
Metal-oxide semiconductor field effect transistors or “MOSFETs” are widely used in modern integrated circuit construction. A MOSFET, in general, comprises a semiconductor substrate, a source electrode and a drain electrode formed therein which have a conductivity opposite to that of the substrate, a gate electrode, and a gate insulation layer such as an oxide layer formed between the substrate and the gate electrode. Hereinafter such a structure is referred to as a “typical surface channel structure” whereby conduction of carriers primarily occurs at or immediately adjacent the surface of the substrate.
Another FET structure provides a buried channel layer formed between the source and the drain electrodes having an opposite conductivity to that of the substrate. Hereinafter this structure is referred to as a “buried channel structure” whereby conduction of carriers primarily occurs within the substrate. Construction of such structures is well known in the art and is not further described here.
A common material used for a gate electrode of a conventional MOSFET is polysilicon. Usually, phosphorus or boron is diffused or implanted, at a high density, into the polysilicon so as to form a gate electrode made of N+ polysilicon or P+ polysilicon in order to lower the resistance of the gate electrode and make stable the work function thereof. Metals having a high melting point such as tungsten, molybdenum or silicides thereof are also well known materials for use as gate electrodes.
The creation of a surface channel MOSFET is well known in the art and is only generally described here. In an N-channel device, the polysilicon gate is N+ doped. Application of a threshold voltage to the gate, which is typically on the order of 0.8 volts, causes the substrate region directly below the gate to undergo inversion whereby the MOSFET adopts a typical surface channel structure. Thereafter, application of a potential between the source and drain acts to drive current between source and drain through this surface channel region. Formation of a surface channel in a P-channel device having a P+ doped gate is accomplished by applying a negative threshold voltage to the gate. Surface channel MOSFETs have a distinct advantage in that they form efficient switches with very little leakage current when subthreshold voltages are applied to the gate.
When a gate potential is applied to surface channel structures, carriers are drawn to the surface of the substrate. Carrier mobility is reduced due to scattering at the surface as the electric field increases. As a result, the operation speed and drive capability of the device are reduced. Further, many hot carriers can be produced in the surface region of the substrate and these hot carriers can be trapped in the interface between the substrate and the gate insulative layer. The trapped carriers cause a change in electrical characteristics of the device thus decreasing its reliability.
A buried channel FET is less subject to the above-described detrimental effects. Buried channel structures can be formed by applying a positive threshold voltage to a polysilicon gate in an N-channel device or a negative threshold voltage to a polysilicon gate in a P-channel device. The buried channel exhibits less surface scattering than the surface channel. The resulting higher carrier mobility leads to reduced resistance and increased conductivity in the device. However, buried channel structures are more sensitive to short channel effects which reduce their effectiveness as switches. These effects include increased leakage current when the MOSFET is “off” and the onset of punchthrough at smaller drain biases as the channel length decreases.
One method for minimizing this short channel effect is disclosed in U.S. Pat. No. 4,841,346 to Noguchi which prescribes selecting a gate electrode material whose Fermi level is located between a conduction band and a valence band of the semiconductor. Another way to increase the drive current of a buried-channel MOSFET is to decrease the gate length of the device. However, these approaches are not always desirable for the reasons described above. Nor are they always feasible due to lithography limitations.
Accordingly, a need remains for a method for manufacturing a MOSFET having improved current flow and efficient switching characteristics.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to provide a novel MOSFET which has a high operation speed, a high carrier mobility, a high current drive capability, and a high reliability.
The invention is a hybrid MOSFET device structure in which part of the channel is a “buried channel” and the remainder of the channel is a conventional surface channel. This structure enables the device to take advantage of the benefits of both technologies: the low series resistance of the buried channel, and the good transistor characteristic of the surface channel. By making the surface channel region relatively short, one can achieve both good transistor switching and leakage characteristics and a higher drive current capability. The hybrid design may be applied to both NMOS and PMOS devices, but can be most useful to increase the drive capability of the PMOS devices in a CMOS process.
A hybrid MOSFET device constructed according to the invention comprises a semiconductor substrate of a first conductivity type and a source and drain region of a second conductivity type formed on the substrate and separated by a channel length. A buried channel region of the second conductivity type is positioned between the source region and drain region. Furthermore, a surface channel region of the first conductivity type is formed between the source region and the drain region in series with the buried channel region, preferably between the buried channel region and the source region.
The method for fabricating the above semiconductor device comprises the steps of forming a transistor structure having a gate electrode, source and drain regions and a gate oxide on a semiconductor substrate. The source and drain regions are laterally separated within the substrate by a channel length. A buried channel region is formed between the source and drain region. Finally, after forming the buried channel region, a surface channel region is formed at a selected location between the source and drain regions and adjacent the buried channel region. The surface channel has a length which is preferably between 20% to 50% of the overall channel length.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.
REFERENCES:
patent: 4841346 (1989-06-01), Noguchi
patent: 4859620 (1989-08-01), Wei et al.
patent: 4901129 (1990-02-01), Hynecek
patent: 5500379 (1996-03-01), Odake et al.
patent: 61-256769 (1986-11-01), None
patent: 62-241378 (1987-10-01), None
Wolf, “Silicon Processing for the VLSI Era, vol. 2: Process Integration”, Lattice Press, Sunset Beach, CA, pp. 309-311 (1990).
Wolf, “Silicon Processing for the VLSI Era, vol. 3: The Submicron Mosfet”, Lattice Press, Sunset Beach, CA, pp. 232-241 and 308-313 (1995).
Aronowitz Sheldon
Henrickson Lindor E.
LSI Logic Corporation
Meier Stephen D.
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