Hybrid semiconductor device with a poly-metal gate structure

Details Hybrid semiconductor device with a poly-metal gate structure Hybrid semiconductor device with a poly-metal gate structure

2001-08-06

2004-08-10

Nguyen, Van Thu (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S324000, C257S326000

Reexamination Certificate

active

06774429

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including memory and logic circuits on the same substrate, and also relates to a method for fabricating a device of that type.
In recent years, a so-called “hybrid device” of the type including memory and logic circuits on the same substrate has been researched and developed vigorously to further increase the operating speed and further improve the performance of a semiconductor memory device.
On the other hand, a technique of forming a “poly-metal gate” as a gate electrode for a transistor by stacking polysilicon and metal films one upon the other is now expected to play a key role in further downsizing and enhancing the performance of a semiconductor integrated circuit device. Accordingly, the implementation of a hybrid device including poly-metal gates is waited for in the art.
Hereinafter, a known method for fabricating a semiconductor memory device will be described with reference to the accompanying drawings.
FIGS. 10A through 10L
illustrate cross-sectional structures corresponding to respective process steps for fabricating a semiconductor memory device including poly-metal gates in memory and logic circuit sections.
First, as shown in
FIG. 10A
, isolation regions
102
are defined in a semiconductor substrate
101
of silicon by embedding silicon dioxide in its surface regions. As a result, multiple active regions, including memory and logic circuit sections
100
and
200
illustrated in
FIG. 10A
, are defined. Thereafter, tunnel insulating and first polysilicon films
103
and
104
are deposited to respective thicknesses of about 9 nm and about 250 nm over the substrate
101
.
Next, as shown in
FIG. 10B
, a capacitive insulating film
105
is formed on the first polysilicon film
104
and then the tunnel insulating, first polysilicon and capacitive insulating films
103
,
104
and
105
are patterned to remove their parts located in the logic circuit section
200
.
Then, as shown in
FIG. 10C
, a gate insulating film
106
is formed on part of the surface of the substrate
101
that has been exposed in the logic circuit section
200
. Subsequently, a second polysilicon film
107
is deposited to a thickness of about 100 nm over the substrate
101
and then doped with phosphorus (P
+
) ions by an ion implantation process.
Next, as shown in
FIG. 10D
, a metal film
108
of tungsten, for example, and a first silicon dioxide film
109
are deposited in this order to respective thicknesses of about 150 nm and about 100 nm over the second polysilicon film
107
.
Thereafter, as shown in
FIG. 10E
, the multilayer structure consisting of the tunnel insulating, first polysilicon, capacitive insulating, second polysilicon, metal and first silicon dioxide films
103
,
104
,
105
,
107
,
108
and
109
are dry-etched while being masked with a resist pattern
110
. The resist pattern
110
defined on the first silicon dioxide film
109
covers not only part of the memory circuit section
100
where a gate electrode should be formed for the memory circuit but also the entire logic circuit section
200
. In this manner, a gate electrode
111
for memory circuit (which will be herein called a “memory gate structure”) is formed.
Subsequently, as shown in
FIG. 10F
, the resist pattern
110
is removed and then source/drain regions
112
and
113
are defined in the substrate
101
using the memory gate structure
111
as a mask.
Then, as shown in
FIG. 10G
, the multilayer structure consisting of the gate insulating, second polysilicon, metal and first silicon dioxide films
106
,
107
,
108
and
109
are dry-etched while being masked with a resist pattern
114
. The resist pattern
114
defined on the first silicon dioxide film
109
covers not only part of the logic circuit section
200
where a gate electrode should be formed for the logic circuit but also the entire memory circuit section
100
. In this manner, a gate electrode
115
for logic circuit (which will be herein called a “logic gate structure”) is formed.
Subsequently, as shown in
FIG. 10H
, arsenic (As
+
) ions are implanted into the substrate
101
using the resist pattern
114
as a mask, thereby defining light-doped source/drain regions (which will be herein called “LDD regions” simply)
116
and
117
in the substrate
101
.
Next, as shown in
FIG. 10I
, after the resist pattern
114
has been removed, a second silicon dioxide film is deposited over the substrate
101
and then etched back, thereby forming sidewall insulating films
118
a
and
118
b
over the memory and logic gate structures
111
and
115
, respectively.
Thereafter, as shown in
FIG. 10J
, a resist pattern
119
is defined to cover the memory circuit section
100
and then As
+
ions are implanted into the substrate
101
using the resist pattern
119
, logic gate structure
115
and sidewall insulating film
118
b
as a mask. In this manner, source/drain regions
120
and
121
are defined for the logic circuit.
Subsequently, as shown in
FIG. 10K
, the resist pattern
119
is removed and then a cobalt film is deposited over the substrate
101
and annealed so that the cobalt film deposited reacts with exposed parts of the substrate
101
. In this manner, a silicide layer
122
is formed on the exposed parts of the substrate
101
.
Finally, as shown in
FIG. 10L
, an interlevel dielectric film
123
of silicon dioxide is deposited over the substrate
101
and then contacts
124
are formed in the interlevel dielectric film
123
so as to make electrical contact with the source/drain regions
112
and
113
and
120
and
121
for the memory and logic circuits. As a result, a semiconductor memory device is completed.
In the known semiconductor memory device, however, the tunnel insulating film
103
of the memory gate structure
111
might show inferior reliability.
Specifically, when the source/drain regions
112
and
113
are defined for the memory circuit by implanting dopant ions into the substrate
101
in the process step shown in
FIG. 10F
, the dopant ions should pass the edges of the memory gate structure
111
. As a result, the tunnel insulating film
103
is partially damaged. For that reason, after the source/drain regions
112
and
113
have been defined, the memory gate structure
111
should be annealed if possible to repair the damage done on the tunnel insulating film
103
.
But if this annealing process were conducted on the memory gate structure
111
, the metal film
108
included in the memory gate structure
111
might be oxidized abnormally and even peel off unintentionally. Accordingly, there has been no other choice than omitting the annealing process. In that case, however, it is impossible to repair the damage done on the tunnel insulating film
103
and it is very hard for such a semiconductor memory device to show good reliability.
Also, where a resistor (not shown) should be formed out of the second polysilicon film
107
in the logic circuit section
200
, the process step of removing part of the metal film
108
deposited on the second polysilicon film
107
should be performed additionally. Thus, the known method is disadvantageous in this respect also.
Furthermore, a hybrid device normally needs a greater area on the chip because a device of that type is essentially a combination of devices of two types. So the known structure interferes with the chip-downsizing trend.
SUMMARY OF THE INVENTION
An object of the present invention is to improve the reliability of a tunnel insulating film for a semiconductor memory device including memory and logic circuits on the same substrate and using a poly-metal gate structure for the logic circuit.
Another object of this invention is to reduce a chip area necessary for a semiconductor memory device of that type.
A third object of the invention is to get a resistor fabricated for a device of that type without increasing the number of process steps needed.
To achieve the first object, in the inventive process for fabricating a semiconductor memory device, i

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