Hybrid semiconductor device having an n+ (p) doped n-type...

Details Hybrid semiconductor device having an n+ (p) doped n-type... Hybrid semiconductor device having an n+ (p) doped n-type...

2006-06-06

2006-06-06

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S213000, C257S288000, C257S402000

Reexamination Certificate

active

07057243

ABSTRACT:
In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

REFERENCES:
patent: 5932919 (1999-08-01), Schwalke
patent: 5953246 (1999-09-01), Takashima et al.
patent: 6216246 (2001-04-01), Shau
patent: 6573169 (2003-06-01), Noble et al.
patent: 6573575 (2003-06-01), Yamazaki

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