Hybrid routing architecture for high density complex...

Details Hybrid routing architecture for high density complex... Hybrid routing architecture for high density complex...

1997-09-30

2003-04-08

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000

Reexamination Certificate

active

06545505

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to programmable logic devices and, more particularly, to signal routing schemes within such devices.
BACKGROUND
Various programmable logic architectures are known, including, for example, Programmable Logic Devices (“PLD”), Programmable Logic Arrays (“PLA”) and Programmable Array Logic (“PAL™”). Although there are many differences between the various architectures, each of the PLD, PLA and PAL architectures typically include a set of input conductors directly coupled as inputs to an array of logical AND gates (“Product Term Array”), the outputs of which, in turn, act as inputs to another portion of the logic device.
FIG. 1
shows a conventional Complex Programmable Logic Device (“CPLD”)
100
which includes a Programmable Interconnect Matrix (“PIM”)
110
and eight logic blocks
120
. Other CPLDs may include different numbers of logic blocks. As shown, CPLD
100
has a total of 262 inputs, each of which is connected to the PIM
110
. The PIM
110
is capable of providing each logic block
120
with its own set of input terms by independently selecting as many as 36 of the possible 262 input signals as input terms for each logic block
120
. The compliments for each of the 36 signals output by the PIM
110
are also provided to each logic block
120
. Thus, each logic block receives as many as 72 input terms from the PIM
110
.
The PIM
110
includes a number of programmable elements (not shown) for controlling an array of multiplexers (not shown) to reduce the total number of programmable elements required. The programmable elements may be volatile memory elements such as static random access memory (“SRAM”), non-volatile memory elements such as flash electrically easrable programmable read only memory (“Flash EEPROM”), or fuses. Alternatively, the programmable elements of the PIM
110
may be implemented to control a matrix of cross point switches; however, this increases the total number of programmable elements required to make the same number of connections. Whether the connections between input conductors and output conductors are provided by cross point switch matrix or by an array of multiplexers, each output conductor can be connected to at least one input conductor. Thus, both forms of connections perform a multiplexing function in the sense of both forms of connection provide for the selection of one of the input conductors from the set of many input conductors.
The 262 inputs to the PIM
110
include 128 feedback signals, 128 input signals and 6 dedicated input signals which include 4 clock signals. Sixteen feedback signals and as many as 16 input signals are provided by each logic block
120
. Each logic block
120
is programmed to perform selected logic functions using sub-combinations of the 72 input terms provided by the PIM
110
. Each logic block
120
has 16 input/output (“I/O”) pins
125
, which may be used as either inputs to the PIM
110
or outputs of the CPLD
100
.
Conceptually, the CPLD
100
may be regarded as a PIM coupled in series with 8 PLDs coupled in parallel, where each individual logic block
120
corresponds to a single PLD. Intermediate stages in the outputs of each of the 8 PLDs are fed back as inputs to the PIM. Depending on the particular set of input signals routed to the outputs of the PIM and the programmed logic functions for each logic block
120
, the 8 PLDs may, in fact, act as two or more PLDs coupled in series with each other. CPLD
100
thus provide a highly versatile logic device.
FIG. 2
shown portions of CPLD
100
in greater detail. Specifically, a logic block
120
is shown as including a product term array
210
, a product term allocator
215
, macrocells
220
and I/O cells
225
. The product term array
210
may be a fully programmable AND array and the product term allocator
215
is configured to allocate product terms from the product term array
210
to 16 macrocells
220
. The product term allocator
215
“steers” product terms to macrocells
220
as needed. For example, if one macrocell requires ten products terms while another requires only three product terms, the product term allocator
215
steers ten product terms to one macrocell and three product terms to the other macrocell. Depending on the configuration, up to 16 product terms can be steered to any one macrocell.
The output for each of the 16 macrocells
220
are fed back to the PIM
110
as input signals. The specific architecture of the macrocells
220
may be any appropriate architecture and each macrocell
220
may include registers and/or buffers. The 16 outputs of the macrocells
220
are also fed to 16 I/O cells
225
. Each of the 16 I/O cells
225
can be programmed to provide output signals to an I/O pin
125
or input signals to the PIM
110
.
CPLD
100
, as shown
FIGS. 1 and 2
, provides a highly versatile programmable logic device. However, as the need for implementing more and more logic functions within digital and/or computer systems has increased, CPLDs of even higher densities have been developed. For example, as shown in
FIG. 3
, CPLD
300
consists of logic blocks connected by two levels of interconnect. Each group of four logic blocks
310
is given its own routing resource, called a Block Interconnect
320
. Together, the four logic blocks
310
and their block interconnect
320
are called a segment
330
. The second level of interconnect, segment interconnect
340
, ties all of the segments
330
together. Segment interconnect
340
also provides a routing path for a number of global clock signals
350
.
Each logic block
310
consists of macrocells, logic arrays, logic allocators, I/O cells and any necessary control signal generators. Thus, each logic block
310
resembles an independent PLD device. In addition to the block interconnect
320
, I/O cells associated with each logic block
310
may have signal paths which feed directly back to that logic block (local feedback paths) which may be used to route signals from the I/O cell back to the logic block. When the signals from an I/O cell are used in another logic block, an interconnect feeder may assign a block interconnect line to that signal. The interconnect feeder may act as an input switch matrix.
The block interconnect
320
and segment interconnect
340
provide connections between any two signals in CPLD
300
. Block interconnect lines and local feedback lines are assigned as required.
Although CPLD
300
provides a high degree of flexibility for implementing logic functions, it also suffers from certain drawbacks. For example, segment interconnect
340
and block interconnect
320
are each multiplexer-based interconnect structures. As such, segment interconnect
340
and block interconnects
320
require significant die area, thus leading to increased fabrication costs for CPLD
300
. Segment interconnect
340
is required to be multiplexer-based because of the need to provide interconnection between every logic block
310
of CPLD
300
. Although such a scheme may provide maximum connectability, it tends to ignore “real-world” designs which typically implement related logic functions in related logic blocks of a segment, thus avoiding the need to transmit numerous signals across an interconnect between segments. What is desired, therefore, is an improved routing architecture for high density CPLDs which avoids such drawbacks.
SUMMARY OF THE INVENTION
The present invention provides scalability for the routing architectures of complex programmable logic devices as they increase in density. A new routing architecture which reduces silicon die area and delay over that of conventional CPLDs, while maintaining the same routing flexibilities for most logic signals within the device, is provided. The novel routing architecture involves the utilization of a two-dimensional network of nonsegmented routing tracks or channels to serve as global interconnects between clusters of logic blocks. Each cluster of logic blocks is a CPLD-like structure which includes a number of logic blocks connected to a local interconnect. Logic

Affiliated with

Also associated with

Rating

Hybrid routing architecture for high density complex... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hybrid routing architecture for high density complex..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid routing architecture for high density complex... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3057346