Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2008-12-12
2010-06-15
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S047000
Reexamination Certificate
active
07737726
ABSTRACT:
A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nonoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux.
REFERENCES:
patent: 6256767 (2001-07-01), Kuekes et al.
patent: 7292498 (2007-11-01), Snider
patent: 7319416 (2008-01-01), Robinett et al.
patent: 7350132 (2008-03-01), Kuekes et al.
patent: 2007/0291524 (2007-12-01), Davis et al.
Reed, M.A., “Molecular-Scale Electronics,”Proceedings of the IEEE, Apr. 1999, pp. 652-658, vol. 87. No. 4.
Rueckes, T. et al., “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing,”Science, Jul. 7, 2000, pp. 94-97, vol. 289, No. 5476.
Whitesides, G.M. et al., “Self-Assembly at All Scales,”Science, Mar. 29, 2002, pp. 2418-2421, vol. 295, No. 5564.
Melosh, N.A. et al., “Ultrahigh-Density Nanowire Lattices and Circuits,”Science, Apr. 4, 2003, pp. 112-115, vol. 300.
Reed, M.A., “Molecular Electronics: Back under control,”Nature Materials, May 2004, pp. 286-287, vol. 3.
Goldstein, S.C. et al., “NanoFabrics: Spatial Computing Using Molecular Electronics,”Proc. Of International Symposium on Computer Architecture, Jul. 2001, pp. 178-189.
Dehon, A., “Array-Based Architecture for FET-Based, Nanoscale Electronics,”IEEE Transactions on Nanotechnology, Mar. 2003, pp. 23-32, vol. 2, No. 1.
Kuekes, P.J. et al., “The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits,”Journal of Applied Physics, 2005, pp. 034301:1-034301:5, vol. 97.
Ziegler, M.M. et al., “CMOS/Nano Co-Design for Crossbar-Based Molecular Electronic Systems,”IEEE Transactions on Nanotechnology, Dec. 2003, pp. 217-230, vol. 2, No. 4.
Kuekes, P.J. et al., “Defect-tolerant interconnect to nanoelectric circuits: internally redundant demultiplexers based on error-correcting codes,”Nanotechnology, 2005, pp. 869-882, vol. 16.
Beckman, R. et al., “Bridging Dimensions: Demultiplexing Ultrahigh-Density Nanowire Circuits,”Science, 2005, pp. 465-468, vol. 310.
Dehon, A., “Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches,”IEEE Transactions on Nanotechnology, Nov. 2005, pp. 681-687, vol. 4, No. 6.
Savage, J.E. et al., “Radial Addressing of Nanowires,”ACM Journal on Emerging Technologies in Computing Systems, Apr. 2006, pp. 129-154, vol. 2, No. 2.
Kuekes, P.J. et al., “Resistor-Logic Demultiplexers for Nanoelectronics Based on Constant-Weight Codes,”Nanotechnology, 2006, pp. 1052-1061, vol. 17.
Snider, G.S. et al., “Crossbar Demultiplexers for Nanoelectronics Based onn-Hot Codes,”IEEE Transactions on Nanotechnology, Mar. 2005, pp. 249-254, vol. 4, No. 2.
Kuekes, P.J. et al., “Effect of Conductance Variability on Resistor-Logic Demultiplexers for Nanoelectronics,”IEEE Transactions on Nanotechnology, Sep. 2006, pp. 446-454, vol. 5, No. 5.
Walls, T.J. et al., “MOSFETs below 10 nm: quantum theory,”Physica E, 2003, pp. 23-27, vol. 19.
Frank, D.J. et al.,“Device Scaling Limits of Si MOSFETs and Their Application Dependencies,”Proceedings of the IEEE, Mar. 2001, pp. 259-288, vol. 89, No. 3.
Likharev, K.K. et al., “CMOL: Devices, Circuits, and Architectures,”Introducing Molecular Electronics, 2005, pp. 447-477, Springer, Berlin, Germany.
Li Shu
Zhang Tong
Rensselaer Polytechnic Institute
Saliwanchilk, Lloyd & Saliwanchik
Tran Anh Q
LandOfFree
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