Hybrid phase locked loop

Details Hybrid phase locked loop Hybrid phase locked loop

1994-09-29

1996-02-27

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 331 17, H03D 324

Patent

active

054955122

ABSTRACT:
A phase locked loop system or other second order feedback system whose natural frequency scales with its output and whose damping factor remains constant includes a filter circuit having a scaling channel for scaling the error, an integrating channel for integrating the error, and a summing circuit for combining the scaled error and integrated error; an integrator circuit responsive to the summing circuit to produce an output signal, the gain of the integrator circuit being proportional to its output signal; and a control circuit for controlling the gain of the integrating channel proportional to the output signal and maintaining constant the ratio of and scaling the product of the unity gained frequency and the zero frequency of the feedback system to keep constant the damping factor and to scale the natural frequency of the feedback system with the output signal, respectively.

REFERENCES:
patent: 4890299 (1989-12-01), Dolivo et al.
patent: 4894734 (1990-01-01), Fischler et al.
patent: 4929918 (1990-05-01), Chung et al.
patent: 5136260 (1992-08-01), Yousefi-Efezei
patent: 5180933 (1993-01-01), Dent
patent: 5258933 (1993-11-01), Johnson et al.
patent: 5319320 (1994-06-01), Abe et al.
Philport et al., "A 7 mbyte/s (65 MHz), Mixed-Signal, Magnetic Recording Channel DSP using Partial Response Signaling With Maximum Likelihood Detection", IEEE Journal, vol. 29, No. 3 Mar. 1994.

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