Hybrid pattern self-testing of integrated circuits

Details Hybrid pattern self-testing of integrated circuits Hybrid pattern self-testing of integrated circuits

1995-06-07

1997-03-18

Nguyen, Hoa T.

Excavating

364717, G01R 3128

Patent

active

056129637

ABSTRACT:
A hybrid random pattern self-test approach is employed in an on-chip fashion to provide desired test signals to circuits on the chip. A simplified weighting circuit is shown to be effective even when only a single bit from a linear feedback shift register is employed for random signal generation. The reduction in linear feedback shift register size and associated weighting circuitry enables the apparatus to be much more readily usable in an on-product configuration thus resulting in significant initial and subsequent test circuit advantages.

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