Hybrid parallel/serial bus interface

Details Hybrid parallel/serial bus interface Hybrid parallel/serial bus interface

2007-07-03

2007-07-03

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S320000, C370S535000, C365S189011, C365S230030, C365S230060

Reexamination Certificate

active

11151006

ABSTRACT:
A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller.

REFERENCES:
patent: 4675861 (1987-06-01), Uttermark
patent: 5018142 (1991-05-01), Simcoe et al.
patent: 5136587 (1992-08-01), Obana et al.
patent: 5327126 (1994-07-01), Beanland
patent: 5347268 (1994-09-01), Nelson et al.
patent: 5400369 (1995-03-01), Ikemura
patent: 5420583 (1995-05-01), Knecht et al.
patent: 5526360 (1996-06-01), Kraft
patent: 5541596 (1996-07-01), Yoshida
patent: 5544319 (1996-08-01), Acton et al.
patent: 5570089 (1996-10-01), Haas
patent: 5592487 (1997-01-01), Knecht et al.
patent: 5602780 (1997-02-01), Diem et al.
patent: 5635933 (1997-06-01), Fitzpatrick et al.
patent: 5784003 (1998-07-01), Dahlgren
patent: 5847578 (1998-12-01), Noakes et al.
patent: 5926120 (1999-07-01), Swenson et al.
patent: 5963638 (1999-10-01), Sheets
patent: 6040792 (2000-03-01), Watson et al.
patent: 6058427 (2000-05-01), Viswanath et al.
patent: 6122683 (2000-09-01), Ku et al.
patent: 6128244 (2000-10-01), Thompson et al.
patent: 6134247 (2000-10-01), Solana de Quesada et al.
patent: 6285960 (2001-09-01), Fung et al.
patent: 6356369 (2002-03-01), Farhan
patent: 6356374 (2002-03-01), Farhan
patent: 6477250 (2002-11-01), Sheets
patent: 6611217 (2003-08-01), Buchanan et al.
patent: 6792003 (2004-09-01), Nair et al.
patent: 6823468 (2004-11-01), Gredone et al.
patent: 6823469 (2004-11-01), Gredone et al.
patent: 6829718 (2004-12-01), Gredone et al.
patent: 6848018 (2005-01-01), Gredone et al.
patent: 6961347 (2005-11-01), Bunton et al.
patent: 42847 (1991-04-01), None
patent: 1997-56528 (1997-07-01), None
“21-Bit Channel Link”, National Semiconductor, Jul. 1997, http://www.national.com/ds/DS/DS90CR21.pdf.
Novak et al., “Channel Link Moving and Shaping Information in Point-To-Point Application”, National Semiconductor, May 1996, http://www.national.com/an/AN/AN-1041.pdf.
von Herzen et al., “Multi-Chanel 622 Mb/s LVDS Data Transfer for Virtex-E Devices”, Xilinx Inc., Jan. 6, 2001, http://direct.xilinx.com/bvdocs/appnotes/xapp233.pdf.
Kitanovska et al., “Bus LVDS with Virtex-E Devices”, Xilinx Inc., Jul. 26, 2000, http://direct.xilinx.com/bvdocs/appnotes/xapp243.pdf.
“DS90CR211/DS90CR212 21-Bit Channel Link”; National Semiconductor; Santa Clara, California; http://www.national.com/ds/DS/DS90CR211.pdf.
Logue, “Virtex SelectLink Communications Channel”; Xilinx, Inc.; San Jose, California; Mar. 15, 2000; http://www.xilinx.com/bvdocs/appnotes/xapp234.pdf.
“LVDS System Data Framing”; Xilinx, Inc.; San Jose, California; Dec. 18, 2000; http://direct.xilinx.com/bvdocs/appnotes/xapp238.pdf.
Goldie, “DS92LV010A Bus LVDS Transceiver Ushers in a New Era of High-Performance Backplane Design”, National Semiconductor, http://www.national.com/an/AN/AN-1115.pdf, Jul. 1998.
Huq et al., “An Overview of LVDS Technology”, National Semiconductor, http://www.national.com/an/AN/AN-971.pdf, Jul. 1998.
“3606—Digitally Controlled Programmable Gain Instrumentation Amplifier”, Burr-Brown Corporation, http://focus.ti.com/lit/ds/symlink/3606.pdf. Oct. 1983.
“DS3886A-BTL 9-Bit Latching Data Transceiver [Obsolete].” http://www.national.com/pf/DS/DS3886A.html May 31, 2006.
“DS90CR213-21-Bit Channel Link -66 MHz.”http://www.national.com/pf/DS/DS90CR213.html May 31, 2006.

Affiliated with

Also associated with

Rating

Hybrid parallel/serial bus interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hybrid parallel/serial bus interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid parallel/serial bus interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3775515