Hybrid MRAM array structure and operation

Details Hybrid MRAM array structure and operation Hybrid MRAM array structure and operation

2002-06-11

2004-06-22

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S063000, C365S173000, C365S230030

Reexamination Certificate

active

06754124

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to magnetoresistive random access memory (MRAM) devices and, more particularly, to read circuitry for such devices.
BACKGROUND OF THE INVENTION
Integrated circuit designers have always sought the ideal semiconductor memory: a device that is randomly accessible, can be written or read very quickly, is nonvolatile, but indefinitely alterable, and consumes little power. Magnetoresistive random access memory (MRAM) technology has been increasingly viewed as offering all these advantages.
A magnetic memory element has a structure which includes ferromagnetic layers separated by a non-magnetic barrier layer that forms a tunnel junction. Information can be stored as a digital “1” or a “0” as directions of magnetization vectors in these ferromagnetic layers. Magnetic vectors in one ferromagnetic layer are magnetically fixed or pinned, while the magnetic vectors of the other ferromagnetic layer are not fixed so that the magnetization direction is free to switch between “parallel” and “antiparallel” states relative to the pinned layer. In response to parallel and antiparallel states, the magnetic memory element represents two different resistance states, which are read by the memory circuit as either a “1” or a “0.” It is the detection of these resistance states for the different magnetic orientations that allows the MRAM to read information.
There are different array architectures that are used within MRAM technology to read memory cells. For instance, one architecture used is the so-called one transistor—one magnetic tunnel junction per cell (“1T-1MTJ”) architecture. This structure is based on a single access transistor for controlling read access to a single magnetic memory element. Another architecture is the cross-point architecture, where the read operation is performed without using an access transistor to control individual memory cells. This type of system uses row and column lines set to predetermined voltages levels to read a selected cell. Each system has its advantages and disadvantages. The cross-point system is somewhat slower in reading than the 1T-1MTJ system, as well as being “noisy” during a read operation; however, the cross-point array has the advantage in that it can be easily stacked for higher density. Additionally, a 1T-1MTJ array is faster, but necessarily less densely integrated than a cross-point array because additional space is needed to supply the 1-to-1 access transistor to memory cell ratio.
It would be desirable to have an MRAM read architecture that could utilize advantages from both the 1T-1MTJ and cross-point architectures while minimizing the disadvantages of each.
SUMMARY OF THE INVENTION
This invention provides an MRAM array read architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and high signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited in the invention by uniquely combining certain characteristics of each. A single access transistor can be used to operate the reading of multiple vertically stacked column segments of MRAM cells. In this architecture, the plurality of column segments each comprise a plurality of standard MRAM cells which share a common sense line, though each MRAM cell can be read individually.


REFERENCES:
patent: 6574135 (2003-06-01), Komatsuzaki
patent: 6606705 (2003-08-01), Volk
patent: 2002/0114206 (2002-08-01), Honigschmid et al.
patent: 2003/0103401 (2003-06-01), Tran et al.

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