Hybrid memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE27104, C257SE21663

Reexamination Certificate

active

07579640

ABSTRACT:
A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.

REFERENCES:
patent: 7030435 (2006-04-01), Gnadinger
patent: 7163886 (2007-01-01), Fujiwara et al.
patent: 2002/0020868 (2002-02-01), Yang et al.
patent: 2002/0024073 (2002-02-01), Shimada et al.
patent: 2002/0163080 (2002-11-01), Taniguchi et al.
patent: 2003/0006443 (2003-01-01), Yang et al.
patent: 2003/0006553 (2003-01-01), Yang et al.
patent: 2003/0173677 (2003-09-01), Yang et al.
patent: 2003-100994 (2003-04-01), None
“Recent Progress in Ferroelectric Memories,” pp. 113-125.
Shoichi Masui, “Applications of Ferroelectric Random Access Memory,” Recent Progress in Ferroelectric Memories, pp. 112-125.

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