Patent
1996-07-01
1999-01-26
Lee, Thomas C.
39520044, 3952006, G06F 1200
Patent
active
058646710
ABSTRACT:
A method, in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes, for servicing a memory access request by a first node of the first plurality of nodes. The memory access request pertains to a memory block of a memory module that has a home node different from the first node in the computer network. The home node has a partial directory cache that has fewer directory cache entries than a total number of memory blocks in the memory module. The method includes the step of ascertaining whether the memory block is currently cached in the partial directory cache. If the memory block is currently cached in the partial directory cache, the first memory access request is serviced using a directory protocol. If the memory block is not currently cached in the partial directory cache, the first memory access request is serviced using a directory-less protocol. The directory states pertaining to copies of the memory block in the network nodes is cached in the partial directory cache when the memory access request generates a renewal point with respect to the directory states.
REFERENCES:
patent: 5055999 (1991-10-01), Frank et al.
patent: 5119481 (1992-06-01), Frank et al.
patent: 5151989 (1992-09-01), Johnson et al.
patent: 5251308 (1993-10-01), Frank et al.
patent: 5297265 (1994-03-01), Frank et al.
patent: 5491817 (1996-02-01), Gopal et al.
patent: 5535116 (1996-07-01), Gupta et al.
patent: 5537569 (1996-07-01), Masubuchi
patent: 5584007 (1996-12-01), Ballard
Archibald, et al., "An Economical Solution to the Cache Coherence Problem", Department of computer Science, FR-35, University of Washington, Seattle, WA.
Grahn, et al., "Efficient Strategies for Software-Only Directory Procotols in Shared-Memory Multiprocessors", Deparment of Computer Engineering, Lund University, 8345 Computer Architecture News, 23 (1995) May, No. 2, New York, US.
Kumar, et al. "Efficient and Scalable Cache Coherence Schemes for Shared Memory Hypercube Mulitprocessors", Department of Computer Science, Texas A&M University, College Station, TX, .COPYRGT. 1994 IEEE.
Farkas, et al., "Scalable Cache consistency for Hierachically Structured Multiprocessors", The Journal of Supercomputing, 8.345-369 (1995) .COPYRGT. 1995 Kluwer Academic Publishers, Boston. Manufactured in the Netherlands.
Lovett, et al., "STiNG: A CC-NUMA Computer System for the Commercial Marketplace," Sequent Computer Systems, Inc., Beaverton, OR, ISCA '96 May 1996 PA, USA .COPYRGT. 1996 ACM 0-89791-786-3/96/0005, pp. 308-317.
O'Krafka, et al., "An Empirical Evaluation of Two Memory-Efficient Directory Methods", Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, The 17 th Annual International Symposium on Computer Architecture, Seattle, WA, May 28-31, 1990, IEEE Computer Society Press, Los Alamitos, Ca, pp. 138-147.
Lenoski, et al., "The Stanford Dash Multiprocessor," The Computer Systems Laboratory at Stanford University, 8153 Computer, 25 (1992) Mar., No. 3, Los Alamitos, CA, US, .COPYRGT. 1992 IEEE, pp. 63-79.
Hagersten Erik E.
Hill Mark Donald
Lee Thomas C.
Sun Microsystems Inc.
Ton David
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