Hybrid interconnect/logic circuits enabling efficient...

Details Hybrid interconnect/logic circuits enabling efficient... Hybrid interconnect/logic circuits enabling efficient...

2005-11-07

2008-05-13

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S047000

Reexamination Certificate

active

07372297

ABSTRACT:
Some embodiments provide a reconfigurable IC that implements a design that is designed at a particular design clock rate. The reconfigurable IC includes reconfigurable circuits for performing operations on a set of inputs in the particular design. The IC further includes routing circuits for routing signals to and from the logic circuits to allow the logic circuits to perform the operations. The reconfigurable IC implements the design by having reconfigurable circuits that reconfigure at a rate faster than the design clock rate. For at least one operation which is defined at the design clock rate, the reconfigurable IC replicates the operation set in at least two reconfiguration cycles to reduce consumption of routing circuits.

REFERENCES:
patent: 5349250 (1994-09-01), New
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5426378 (1995-06-01), Ong
patent: 5521835 (1996-05-01), Trimberger
patent: 5600263 (1997-02-01), Trimberger et al.
patent: 5610829 (1997-03-01), Trimberger
patent: 5629637 (1997-05-01), Trimberger et al.
patent: 5646545 (1997-07-01), Trimberger et al.
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5701441 (1997-12-01), Trimberger
patent: 5737235 (1998-04-01), Kean et al.
patent: 5815726 (1998-09-01), Cliff
patent: 5825662 (1998-10-01), Trimberger
patent: 5889411 (1999-03-01), Chaudhary
patent: 6069490 (2000-05-01), Ochotta et al.
patent: 6084429 (2000-07-01), Trimberger
patent: 6091263 (2000-07-01), New et al.
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6184709 (2001-02-01), New
patent: 6292019 (2001-09-01), New et al.
patent: 6346824 (2002-02-01), New
patent: 6480954 (2002-11-01), Trimberger et al.
patent: 6496918 (2002-12-01), DeHon et al.
patent: 6526559 (2003-02-01), Schiefele et al.
patent: 6529040 (2003-03-01), Carberry et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6829756 (2004-12-01), Trimberger
patent: 6998872 (2006-02-01), Chirania et al.
patent: 7028281 (2006-04-01), Agrawal et al.
patent: 7075333 (2006-07-01), Chaudhary et al.
patent: 7109752 (2006-09-01), Schmit et al.
patent: 7138827 (2006-11-01), Trimberger
patent: 7157933 (2007-01-01), Schmit et al.
patent: 2002/0125910 (2002-09-01), New et al.
U.S. Appl. Nos. 11/269,869, 11/269,858, and 11/269,518.
Andraka Consulting Group, Inc., “Multiplication in FPGAs,” http://www.andraka.com/multipli.htm, Jan. 25, 2006, pp. 1-7.
Chiricescu, S., et al., “Morphable Multipliers,”FPL 2002, LNCS 2438, Sep. 2002, pp. 647-656, Springer-Verlag Berlin Heidelberg.
Dehon, A., “Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density,”Proceedings of the Fourth Canadian Workshop on Field-Programmable Devices, May 1996, pp. 47-54.
Dehon, A., “Transit Note #121: Notes on Programmable Interconnect,”M.I.T. Transit Project, Feb. 1995, pp. 1-13.
Dehon, A., et al., “Reconfigurable Computing: What, Why, and Implications for Design Automation,”DAC1999, Jun. 1999, ACM, New Orleans, Louisiana.
Giraud-Carrier, C., “A Reconfigurable Data Flow Machine for Implementing Functional Programming Languages,”SIGPLAN Notices, Sep. 1994, vol. 29 (9): 22-28.
Hauck, S., et al., “High-Performance Carry Chains for FPGAs,”FPGA98, Feb. 1998, pp. 223-233, ACM, Monterey, California, USA.
Sheeran, M., “Generating Fast Multipliers Using Clever Circuits,” NPL Date Unknown.
Trimberger S., “Effects of FPGA Architecture in FPGA Routing,” 32ndACM/IEEE Design Automation Conference, Jun. 1995, ACM.
Xing, S., et al., “FPGA Adders: Performance Evaluation and Optimal Design,”IEEE Design & Test of Computers, Jan.-Mar. 1998, pp. 24-29, IEEE.

Affiliated with

Also associated with

Rating

Hybrid interconnect/logic circuits enabling efficient... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hybrid interconnect/logic circuits enabling efficient..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid interconnect/logic circuits enabling efficient... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3983750