Hybrid integrated circuit device having burn-in testing means

Details Hybrid integrated circuit device having burn-in testing means Hybrid integrated circuit device having burn-in testing means

1993-10-14

1995-02-28

Saadat, Manshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257401, 257723, 257786, H01L 2166, H01L 2316, H01L 3902, H01L 2978

Patent

active

053939913

ABSTRACT:
A highly reliable hybrid integrated circuit device includes at least one bare chip power MOS-FET and a control IC for controlling the power MOS-FET, both mounted on a circuit substrate. A burn-in test voltage supply line supplies a burn-in test voltage to a gate terminal of the power MOS-FET for a burn-in test. Where a plurality of MOS-FETs are present, burn-in test voltage supply lines connect the gate terminals of the power MOS-FETs to each other. The supply lines are severed to electrically separate the gate terminals from each other after the burn-in test is completed. Alternatively, resistors having a predetermined resistance are inserted in the supply lines so that normal operation, after the burn-in test, is not affected by the gate connections.

REFERENCES:
patent: 5036380 (1991-01-01), Chase
Goodman et al. 1 IBM Technical Disclosure Bulletin, "Pad Deletion Test Technique", vol. 26, No. 10A, Mar. 1984, pp. 4889-4890. l
IBM Tehnical Disclosure Bulletin, vol. 36, No. 08, Aug. 1993, pp. 223-224.

Affiliated with

Also associated with

Rating

Hybrid integrated circuit device having burn-in testing means does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hybrid integrated circuit device having burn-in testing means, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid integrated circuit device having burn-in testing means will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-850031