Hybrid IGBT and MOSFET for zero current at zero voltage

Details Hybrid IGBT and MOSFET for zero current at zero voltage Hybrid IGBT and MOSFET for zero current at zero voltage

2000-05-05

2003-09-30

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S379000, C257S391000, C257S544000

Reexamination Certificate

active

06627961

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to MOSgated transistors and more specifically relates to a hybrid transistor consisting of the parallel connection of an IGBT and a power MOSFET.
BACKGROUND OF THE INVENTION
MOSgated transistors such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBTs) are well known and have numerous advantages over conventional junction type bipolar transistors, including a simpler drive circuit. However, in certain applications, for example, for the drive of a CRT or TV deflection coil, a high voltage MOSFET has too high an on-resistance, while an IGBT forward conduction characteristic does not provide the necessary linearity near zero voltage and zero current.
It would be desirable to provide a MoSgated device for use in high voltage (for example, 1,500 volts) circuits and which exhibit good linear behavior at low voltage and low current.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the invention, a parallel connected power MOSFET and IGBT are used to define a high voltage MOSgated transistor which will have the low forward voltage drop of the IGBT and the linearity of the MOSFET at low voltage whereby the device can be used in place of a bipolar transistor in a TV deflection coil drive circuit or the like.
The novel device can be implemented by a copacked IGBT and power MOSFET die in a common package, as in the manner of the Schottky diode and MOSFET die in U.S. Pat. No. 5,814,884; or the MOSFET and IGBT can be integrated into a common die. In either case, the total MOSFET area is preferably about 50% that of the IGBT area and can range from 10% to 100%.
In a preferred integrated embodiment of the invention, a conventional D-MOS structure is formed on the top surface of an N
−
silicon die. The D-MOS structure spaced bases are then aligned vertically with alternate N
+
MOSFET contact regions and P
+
IGBT collector regions. The N
+
contact regions and P
+
collector regions are preferably spaced by about a 1 minority carrier diffusion length. These regions may be activated as by a laser anneal. A single bottom contact, preferably aluminum, then contacts the bottom regions to complete the integrated device.


REFERENCES:
patent: 4901127 (1990-02-01), Chow et al.
patent: 5178370 (1993-01-01), Clark et al.
patent: 5569982 (1996-10-01), Nadd
patent: 5689208 (1997-11-01), Nadd
patent: 5814884 (1998-09-01), Davis et al.
patent: 5851857 (1998-12-01), Kelberlau et al.
patent: 5900662 (1999-05-01), Frisina et al.

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