Hybrid E.sup.2 cell and related array

Details Hybrid E.sup.2 cell and related array Hybrid E.sup.2 cell and related array

1983-05-31

1986-03-18

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365189, G11C 1300

Patent

active

045772959

ABSTRACT:
An improved MOS E.sup.2 cell is described which includes a floating gate and a thin oxide region. Charge injected into the substrate is used to program the floating gate by hot electron injection through the tunnel oxide region. Erasing is accomplished by tunneling through the thin oxide region. With this arrangement, the capacitance coupling between the floating gate and control gate is greatly reduced, allowing the cell to be substantially smaller. Several novel inhibit modes permit the fabrication of an array without using a selection device for each of the cells.

REFERENCES:
patent: 4435790 (1984-03-01), Tickle et al.

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