Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-27
2003-07-08
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000
Reexamination Certificate
active
06590264
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a diode structure and its application. In particular, the present invention relates to a diode structure with electrostatic discharge (ESD) robustness.
2. Description of the Related Art
A conventional P-type diode (Dp) realized in the CMOS process with STI isolation technology is shown in
FIG. 1
, where a P+ diffusion
10
(as the anode) is placed in an N-well
12
to form the P-N junction of the diode. The N+ diffusion
16
in the N-well
12
acts as the cathode of the P-type diode. The P+ diffusion
10
is surrounded by a shallow trench isolation (STI) region
18
and isolated from the N+diffusion
16
. In contrast, the N-type diode (Dn) realized in the CMOS process with STI technology is shown in
FIG.2
, where an N+ diffusion
20
(as the cathode) is placed in a P-well
22
to form the P-N junction of the diode. P+ diffusion
24
in the P-well
22
acts as the anode of such an N-type diode. There is a STI region
28
between the P+ and N+ diffusions
24
and
20
to isolate the two diffusions.
When such a P-type or N-type diode is stressed by ESD voltage in a reverse-biased condition, the P-N junction adjacent to the STI boundary is easily damaged, resulting in low ESD robustness.
To overcome the ESD vulnerable location adjacent to the STI boundary, a modified P-type diode structure is provided in U.S. Pat. No. 5,811,857 by IBM (international business machine), as shown in FIG.
3
. Compared to
FIG. 1
, the STI regions between the P+ and N+ diffusions
30
and
36
are replaced by a poly gate
32
. During P+ implantation, P+ diffusion
30
and portion
34
of the poly gate
32
are doped. During N+ implantation, N+ diffusion
36
and portion
38
of the poly gate
32
are doped. Similarly, the N-type diode structure in U.S. Pat. No. 5,811,857 is formed as shown in FIG.
4
. The P-N junction of the P-type or N-type diode shown in
FIG. 3
or
4
has no contact with STI boundary. Therefore, the ESD vulnerable location adjacent to STI does not appear and such modified diodes in
FIGS. 3 and 4
sustain higher ESD stress compared to the traditional diode structures in
FIGS. 1 and 2
.
SUMMARY OF THE INVENTION
The object of the present invention is to provide hybrid diode structures and their applications on ESD protection. The hybrid diodes of the present invention have excellent ESD robustness.
According to the object, the present invention provides a hybrid diode comprising a first semiconductor layer, a gate structure, a first N-type diffusion region, a second N-type diffusion region, a first P-type diffusion region, a second P-type diffusion region, and an inter-connection. The gate structure is formed on the first semiconductor layer with a second semiconductor layer stacked on an isolating layer. The first N-type diffusion region is formed on the first semiconductor layer adjacent to the gate structure. The second N-type diffusion region is formed on the second semiconductor layer. The first and the second N-type diffusion regions are formed with the same N-type implantation. The first P-type diffusion region is formed on the first semiconductor layer adjacent to the gate structure. The second P-type diffusion region is formed on the second semiconductor layer. The first and the second P-type diffusion regions are formed with the same P-type implantation. The first N-type diffusion region and the first P-type diffusion region are respectively the cathode and anode of a first diode. The second N-type diffusion region and the second P-type diffusion region are respectively the cathode and anode of a second diode. The inter-connection connects the first and second diodes in parallel or in series to form the hybrid diodes.
The hybrid diodes of the present invention are used between two pads to provide ESD protection between the two pads. The pads can be power lines, I/O pads or a combination of the two. The hybrid diodes can be either forward-biased or reverse-biased during normal conditions. The hybrid diodes can also be used between different power lines to form ESD-connection cells, which provide electrical connection during an ESD event.
The series hybrid diodes of the present invention have smaller equivalent capacitance, and are specially designed for ESD protection of the I/O ports of radio frequency (RF) ICs. The parallel hybrid diodes of the present invention have lower operating resistance and sustain higher ESD stress.
According to the object, the present invention further provides an electrostatic discharge (ESD) protection system suitable for use in an integrated circuit (IC). The ESD protection system comprises a relatively high voltage ESD bus, a relatively low voltage ESD bus, a power rail ESD clamp bus coupled between the relatively high voltage ESD bus and the relatively low voltage ESD bus, a high voltage ESD-connection cell coupled between the relatively high voltage ESD bus and a high voltage power line, and a low voltage ESD-connection cell coupled between the relatively low voltage ESD bus and a low voltage power line. A hybrid diode is formed in at least one of the high and low voltage ESD-connection cells. The hybrid diode has the structure described hereinabove.
REFERENCES:
patent: 5811857 (1998-09-01), Assaderaghi et al.
patent: 2002/0084490 (2002-07-01), Ker et al.
Chuang Che-Hao
Ker Ming-Dou
Lin Geeng-Lih
Intellectual Property Solutions Incorporated
Prenty Mark V.
Vanguard International Semiconductor Corporation
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