Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-17
2001-04-24
Teska, Kevin J. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06223329
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer-aided circuit design including automatic placement and routing of integrated circuits and field-programmable gate arrays and, in particular, to a particularly efficient mechanism by which particularly large and complex circuits can be more efficiently designed to a layout level.
BACKGROUND OF THE INVENTION
Many electrical circuits manufactured today are extremely complex and include, for example, many millions transistors and digital logic gates. Circuit complexity has greatly surpassed the capacity of manual design techniques and all but the simplest of modern electrical circuits are designed using computer aided design systems.
Circuit complexity is also challenging the available resources of even the largest, most sophisticated computer-aided automatic layout place and route design systems as well. In general, there are primarily two paradigms by which automatic layout place and route design systems are used by engineers to design electrical circuits layout. The first is called the flat paradigm. In the flat paradigm, the circuit under design is represented entirely at a physical layout abstraction level such that individual standard logic gates and cells are placed directly on a floor map and lines between such standard gates and cells are routed directly within the floor map by automatic layout techniques. The advantage of the flat paradigm is relative ease in optimizing placement of gates and cells and routing of connections between such gates and cells. The disadvantage of the flat paradigm is that the computer resources and computing time required to effect changes in a design increase exponentially with increases of complexity of the circuit under design and can quickly overwhelm the computer capacity and a project design schedule. For example, placing gates and cells of a moderately complex circuit, e.g., having about 200,000 such gates and cells, can take several hours of processing time on relatively high-power workstation computer systems such as the UltraSPARC workstation available from Sun Microsystems, Inc. of Palo Alto, Calif. Routing of lines between such gates and cells of such a circuit can require several days of processing time on the same workstation computer system.
Performing placement and routing according to the second paradigm, i.e., the hierarchical paradigm, requires substantially less computer processing resources than does performing placement and routing according to the flat paradigm. In the hierarchical paradigm, circuit elements which include gates and cells are combined into functional blocks such that the functional blocks serve as abstractions of underlying circuit elements. Such functional blocks can be combined into larger, more abstract, functional blocks of a higher level of a hierarchy. For example, a computer processor can be designed as including a relatively small number of functional blocks including a memory management block, an input/output block, and an arithmetic logic unit. The arithmetic logic unit can be designed to include a relatively small number of functional blocks including a register bank, an integer processing unit, and a floating point processing unit. The integer processing unit can include sub-blocks such as an adder block, a multiplier block, and a shifter block. At the lowest level of the hierarchical design specification, blocks are individual circuit elements such as flip-flops and digital logic gates.
The primary advantage of the hierarchical paradigm is that circuit design engineers can design complex circuits by designing relatively small functional blocks and using such designed blocks to build bigger blocks. In other words, the seemingly insurmountable job of designing a highly complex circuit is divided into small, workable design projects. In addition, functional blocks designed for one circuit can be used as components of a different circuit, thereby reducing redundant effort by the engineers.
In general, fewer computer processing resources are required for placement of circuit elements and routing of connections between the elements according to the hierarchical paradigm rather than according to the flat paradigm. Such is generally true since network routing is typically performed at a particular level of the hierarchy prior to replacing blocks at the level with the component sub-blocks of the blocks. As a result, the networks to be routed at any particular level is typically significantly more simple than networks to be routed in a flat paradigm, i.e., all networks of the circuit.
The primary disadvantage of the hierarchical paradigm is that accuracy and detail in global network routing suffers substantially. For example, routing a network at the highest level is generally based on an approximate placement of elements of blocks of the circuit design since such elements are not actually placed until lower levels of the hierarchy are processed. In some instances, networks are routed only to a block and are not further routed, i.e., to an individual element within the block, until lower levels of the hierarchy are processed. Such makes minimization of signal skew, i.e., different arrival times of a single signal at different gates and/or cells of the circuit, particularly difficult within the hierarchical paradigm. There are several conventional ways to minimize timing delay skews of such global networks, including “Clock-Tree-Synthesis” which requires that the circuit design under development be “flat” to minimize the timing delay skew. In fact, signal skew is generally best minimized according to the flat paradigm in which placement of individual gates and cells can be more directly controlled. Global network routing is particularly difficult in hierarchical circuit designs since, in such hierarchical designs, functional blocks are somewhat abstract and placement of elements within such functional blocks are soft, i.e., are not yet precisely fixed.
What is needed is a system by which a hierarchical design can be more efficiently and accurately rendered to a layout-level circuit specification to thereby provide the advantages of both the flat and hierarchical paradigms.
SUMMARY OF THE INVENTION
In accordance with the present invention, a hierarchical circuit design is divided into independent components which can be processed independently of one another to simultaneously achieve the advantages of both hierarchical and flat paradigms. In particular, blocks of the hierarchical circuit design are flattened sufficiently to place and route global networks through the blocks. The flattened blocks of the hierarchical circuit design are then de-coupled to form independent blocks. In de-coupling the blocks, pins are added at intersections of the global networks with boundaries of the blocks. The global networks are divided into wire fragments between the pins and components of the flattened circuit design in generally the same place previously occupied by the global networks. Accordingly, placement, routing, and network timing of the global networks are accurately represented and preserved by the wire fragments. Wire fragments which are inside a particular block of the circuit design are added to the block. Wire fragments which are outside all blocks are fixed as components of the circuit design. The blocks are therefore de-coupled at the pin positions along the block boundaries.
As a result, each block of the hierarchical circuit design can be reconstructed into a hierarchical representation, complete with newly added wire fragments of the global networks, independently of all other blocks of the hierarchical circuit design. For example, another block can be left in the flattened state and processed according to a flat paradigm while the former block is reconstructed to a hierarchical representation and processed according to a hierarchical paradigm. A circuit design engineer is free to employ whichever paradigm is most suitable to a particular component of the hierarchical circuit design irrespective of which paradigm is most suitable to oth
Ling Zhang Qiao
Zhen Cai
Ivey James D.
Kik Phallaka
Prosper Design Systems Pte. Ltd.
Teska Kevin J.
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