Hybrid compensated buffer design

Details Hybrid compensated buffer design Hybrid compensated buffer design

2005-07-26

2005-07-26

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C326S033000, C326S034000, C326S087000

Reexamination Certificate

active

06922077

ABSTRACT:
According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the devices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.

REFERENCES:
patent: 5559441 (1996-09-01), Desroches
patent: 6133749 (2000-10-01), Hansen et al.
patent: 6486698 (2002-11-01), Yanagawa
patent: 2001/0000951 (2001-05-01), Welch et al.
patent: 2002/0101278 (2002-08-01), Schultz et al.
patent: 0 913 943 (1999-06-01), None
PCT Written Opinion, PCT Search Report, PCT/US2004/018417, 8 pages. Sep. 6, 2004.

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