Hybrid CMOS-bipolar memory cell

Details Hybrid CMOS-bipolar memory cell Hybrid CMOS-bipolar memory cell

1988-12-12

1992-08-04

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365177, G11C 700

Patent

active

051365359

ABSTRACT:
A hybrid CMOS-bipolar memory cell for a high speed memory includes a CMOS latch which has two storage nodes (104) and (106) for storing two logic states. The CMOS latch is disposed between a high voltage node (110) and a low voltage node (114). The two nodes are maintained at a predetermined voltage to maintain a static state. A bipolar current drive transistor (120) is provided which is connected to one of the storage nodes (106) to provide a low source impedance for output from the memory cell. A work line (44) is connected to the high voltage node (110) for selection thereof by varying between two predetermined voltages. The cell is written to be selectively discharging either node (104) or (106) to a low voltage node (114) through bipolar transistors (122) and (124). The bipolar transistor (122) and (124) provide high transconductance switches for selectively discharging the storage nodes (104) and (106).

REFERENCES:
patent: 4004284 (1977-01-01), Heeren
patent: 4594688 (1986-06-01), Uno
patent: 4701883 (1987-10-01), Wrathall et al.
patent: 4779230 (1988-10-01), McLaughlin et al.
A 4 nsec 4Kx1bit Two-Port BiCMOS SRAM by T. S. Yang et al. Center for Integrated Systems, Stanford Univ. May 1988.

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