Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2007-04-17
2007-04-17
An, Meng-Al T. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
10268233
ABSTRACT:
A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry signals. In a method for producing a carry logic circuit, a group generate logic function GI, I+1=GIOR GI+1AND PIis to be performed. When GI+1=CI+1, GI, I+1=CI, arrival times of generate signals GIand GI+1, are investigated. If GIarrives before GI+1, a complex AND-OR-INVERT gate is used, otherwise a cascaded pair of NAND gates is selected. To produce a complementary carry signal, a logic function GI, I+1′=GI′ AND GI+1′ OR PI′ is to be performed. If the generate signal GI′ arrives before GI+1′, a complex OR-AND-INVERT gate is used, otherwise a cascaded pair of NOR gates is selected.
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Kyung-Nam et al., A New Adder Scheme with Reduced P, G Signal Generations using Redundant Binary Number System, IEEE International Symposium on Circuits and Systems, May 28-31, 2000.
An Meng-Al T.
Carr LLP
Do Chat C.
Rifai D'Ann
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