Hybrid cache/SIRO buffer system

Details Hybrid cache/SIRO buffer system Hybrid cache/SIRO buffer system

1998-04-30

2001-06-26

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S110000, C712S207000

Reexamination Certificate

active

06253288

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods and apparatus for improving memory read performance in computer systems, and relates particularly to cache systems, FIFO buffers and the like.
BACKGROUND
Memory read efficiency is an important benchmark for measuring the performance of most computer systems and their memory intensive subsystems. Because high speed memory systems are typically more expensive to implement than low speed memory systems, most designers utilize a hierarchy of memory speeds in order to achieve a balance between price and performance. For example, large volume storage needs may be met using a low cost, low speed device such as a magnetic or optical disk. Intermediate volume storage needs may be met using static or dynamic random access memory (“RAM”), which has an intermediate cost and response time. A cache memory may be used to enhance system performance by providing very small volume storage capacity but with very fast response time. Unfortunately, cache memory is the most expensive type to implement because of the high cost of high speed RAM and the relatively large overhead associated with cache system control circuitry and algorithms.
Another type of memory arrangement typically found in computer systems is the well known first-in-first-out (“FIFO”) buffer. A FIFO buffer is useful, for example, in providing a data path between subsystems having different or varying data transfer speeds. While a FIFO buffer is relatively inexpensive to implement, its applications are limited by its simplicity.
In some contexts, none of the above memory systems can yield satisfactory performance at a satisfactory price. One such context is found in graphics subsystems wherein reads of data by a host processor from a frame buffer or other memory are common. Typically, such data reads in the aggregate are intended to retrieve data that are stored in a contiguous block of addresses. Frequently, however, the read commands are not issued by the host processor in perfect address order. Instead, they are merely “weakly” ordered. If the data reads were issued in perfect address order, then performance enhancement could be achieved inexpensively in such a context by fetching ahead and placing speculatively read data in a FIFO buffer. But if the read commands are not issued in perfect address order, such a solution would not perform well because the FIFO buffer would have to be flushed each time a break occurred in the sequence of addresses requested by the read commands. While a traditional cache memory could be used to achieve a performance enhancement in the case of weakly-ordered reads, the expense and overhead of a traditional cache memory solution could not easily be justified for solving such a special-case problem in such a special-purpose computer subsystem.
Therefore, a need exists for a relatively inexpensive memory arrangement that will yield a performance improvement in cases wherein read commands are issued to retrieve data that are stored at contiguous addresses, but wherein the read commands are not issued in perfect address order.
SUMMARY OF THE INVENTION
The invention includes numerous aspects, each of which contributes to improving read performance when read commands are issued by a host system intending to retrieve data that are stored at contiguous addresses in memory, but when the host system does not issue the read commands in perfect address order.
In one aspect, the invention includes a hybrid cache/SIRO buffer system. Responsive to a first read request by a host system, the cache/SIRO buffer begins to retrieve data from memory. It first retrieves data from an address that is equal to or close to the address associated with the first read request; but then it also retrieves data from subsequent addresses, regardless of whether the subsequent addresses were actually requested by the host system. In other words, the cache/SIRO buffer speculatively reads ahead. Data that have been stored in the cache/SIRO buffer system are available to be accessed randomly. As read requests from the host system continue to be processed by the cache/SIRO buffer system, more speculative reads are executed by the cache/SIRO buffer system until the buffer is nearly full of data. Once near-fullness occurs, low-address data in the buffer are overwritten with new data.
Thus, the cache/SIRO buffer system effectively opens a memory window beginning with an address equal to or near the first address requested by the host system, and then moves the memory window forward as further read requests from the host system are processed. In this manner, a traveling window to memory is provided. If the host system begins requesting data from an address region not covered by the window and the out-of-window requests result in a threshold number of buffer “misses,” then the buffer reinitializes itself. Upon reinitialization, the cache/SIRO buffer system effectively opens a new memory window corresponding to the new range of addresses being requested by the host system.


REFERENCES:
patent: 5526511 (1996-06-01), Swenson et al.
patent: 5584038 (1996-12-01), Papworth et al.
patent: 5586294 (1996-12-01), Goodwin et al.
patent: 5918045 (1999-06-01), Nishii et al.
patent: 5983321 (1999-11-01), Tran et al.

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