Hybrid cache coherence using fine-grained hardware message...

Details Hybrid cache coherence using fine-grained hardware message... Hybrid cache coherence using fine-grained hardware message...

2011-02-22

2011-02-22

Chery, Mardochee (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S143000, C711SE12039

Reexamination Certificate

active

07895400

ABSTRACT:
Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware.

REFERENCES:
patent: 6505277 (2003-01-01), Arimilli et al.
patent: 6865695 (2005-03-01), Joyner et al.
patent: 2005/0097147 (2005-05-01), Hunt et al.
Kavi, Krishna, Kim, Hyong-Shik, Lee, Ben, Hurson, Ali, Shared Memory and Distributed Shared Memory Systems: A Survey, University of Alabama, Oregon State University, Penn State University, No Date, pp. 19.
Hennessy, John, Heinrich, Mark, Gupta, Anoop, Cache-Coherent Distributed Shared Memory: Perspectives on Its Development and Future Challenges, IEEE, Proceedings of the IEEE, vol. 87, No. 3, Mar. 1999, pp. 418-429.
Roy, Sumit, Chaudhary, Vipin, Strings: A High-Performance Distributed Shared Memory for Symmetrical Multiprocessor Clusters, TR-98-02-47, Parallel and Distributed Computing Laboratory, Wyane State University, No Date. pp. i, 1-11.
Heinlein, John, Gharachorloo, Kourosh, Dresser, Scott, Gupta, Anoop, Integration of Message Passing and Shared Memory in the Stanford FLASH Multiprocessor, Computer Systems Laboratory, Stanford University, http://www-flash.stanford.edu/architecture/papers/flash—msg/, printed Feb. 21, 2007, pp. 28.
Scales, Daniel J., Gharachorloo, Kourosh, Thekkath, Chandramohan A., Shasta: A Low Overhead, Software-Only Approach for Supporting Fine-Grain Shared Memory, Western Research Laboratory; Systems Research Center, Digital Equipment Corp., ASPLOS VII, Oct. 1996, pp. 174-185.
Kontothanassis, Leonidas I., Scott, Michael L., Software Cache Coherence for Large Scale Multiprocessors, Department of Computer Science, University of Rochester, First IEEE Symposium on High-Performance Computer Architecture, Jan. 22-25, 1995, pp. i-ii, 286-295.
Li, Kai, Ivy: A Shared Virtual Memory System for Parallel Computing, Department of Computer Science, Princeton University, No Date, pp. 94-101.
Radovic, Zoran, Software Techniques for Distributed Shared Memory, Uppsala Universitet, Nov. 18, 2005, pp. i-iv, vii-xi, 1-121.

Affiliated with

Also associated with

Rating

Hybrid cache coherence using fine-grained hardware message... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hybrid cache coherence using fine-grained hardware message..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid cache coherence using fine-grained hardware message... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2644313