Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S067000, C257S347000, C257S354000, C365S154000, C365S156000

Reexamination Certificate

active

11108012

ABSTRACT:
The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

REFERENCES:
M. Yang, et al., IEDM 2003.
J. Tschanz, et al., IEEE Journal of Solid State Circuits, vol. 37, No. 11, pp. 1396-1402, Nov. 2002.
M. Yang, et al., “High-Performance CMOS SOI Devices on Hybrid Crystal Oriented Substrates”. IEDM 2003.
J. Tschanz, et al. “Adaptive Body Bias For Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage” IEEE Journal of Solid-State Circuits, vol. 37, No. 11, pp. 1396-1402, Nov. 2002.

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