Hybrid bulk/silicon-on-insulator multiprocessors

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S499000

Reexamination Certificate

active

06864524

ABSTRACT:
A multiprocessor integrated circuit is disclosed. A preferred embodiment of a multiprocessor chip has microprocessors formed on silicon-on-insulator regions and dynamic random access memory level-2cache memories or level-3 cache memories formed on bulk regions of the chip. A preferred embodiment includes a redundant architecture having a signal bus for coupling the microprocessors to the level-2 or level-3 cache memories in which the signal bus includes a programmable selector circuit for bypassing defective microprocessors or defective level-2 or level-3 cache memories.

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Rudack et al. “Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM” International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 1-3, 1999. IEEE, pp. 31-39.*
Crowder, S. et al. “An Embedded DRAM High Performance 0.18 um Logiv Technology with Copper Beol” 1998 Int'l Electron Devices Meeting. Technical Digest. Dec. 6-9, 1998.*
Bernstein, K. et al. SOI Circuit Design Concepts. Kluwer Acadmic Publishers, 2000. TK7871.99M44B48 2000.

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