Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2007-04-24
2009-10-06
Vo, Don N (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S159000, C331S025000, C332S128000
Reexamination Certificate
active
07599462
ABSTRACT:
A hybrid analog/digital phase-lock loop with high-level event synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level and synchronizing the output clock to high-level events. A numerically-controlled analog oscillator provides a clock output and a counter divides the frequency of the clock output to provide input to a digital phase-frequency detector for detecting an on-going phase-frequency difference between the timing reference and the output of the counter. A synchronization circuit detects or receives a high-level event signal, and resets the on-going phase-frequency difference and optionally the counter to synchronize the clock output with the events. The synchronization circuit may have an arming input to enable the synchronization circuit to signal a next event. Another clock output divider may be included to generate a timing reference output, and the other clock divider also reset in response to a detected event.
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Cirrus Logic Inc.
Harris Andrew M.
Mitch Harris Atty at Law, LLC
Vo Don N
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