Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-23
2001-05-08
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C438S246000, C438S249000
Reexamination Certificate
active
06229173
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to have a vertical transistor having a buried surface strap.
2. Description of the Related Art
Vertical transistors are known in the art of semiconductor manufacturing for reducing the overall size of the transistor device and, therefore, for allowing an increase in the scaling of such devices. However, conventional vertical transistors have substantial problems associated with the formation of the strap (e.g., the conductive connection between the storage device and the gate/drain of the transistor).
The invention overcomes these problems by forming a self-aligned buried strap within a vertical transistor, as specified below.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for manufacturing an integrated circuit chip which includes forming a storage capacitor in a vertical opening in a horizontal substrate forming a conductive strap laterally extending from the vertical opening and forming a transistor having a channel region extending along a vertical surface, the vertical surface lying outside of and being laterally displaced from the vertical opening, the transistor being electrically connected to the storage capacitor by an outdiffusion of the conductive strap.
The forming of the conductive strap includes removing an upper portion of an insulator surrounding the storage capacitor to form a strap gap and filling the strap gap with a conductive material. The forming of the transistor includes lithographically forming a gate opening in the substrate over the storage capacitor, the gate opening having at least one wall laterally displaced from the vertical opening, wherein the wall of the gate opening includes the vertical surface. The invention also includes forming first spacers in the gate opening and forming a strap opening in the substrate using the first spacers to align the strap opening, wherein the conductive strap is formed by forming second spacers in the strap opening. This process further includes removing the first spacers and a portion of the second spacers to form a step, the outdiffusion being formed in a portion of the step adjacent the conductive strap. The gate opening is wider than the strap opening, thereby forming the step.
The invention forms a gate conductor adjacent the vertical surface, wherein a voltage in the gate conductor makes the channel region conductive, electrically connecting the transistor and the storage capacitor via the conductive strap and the outdiffusion.
Another embodiment of the invention includes forming a storage capacitor in a vertical opening in a horizontal substrate, forming a step in the vertical opening above the storage capacitor, forming a conductive strap along a lower portion of the step, the conductive strap being electrically connected to the storage capacitor and laterally extending from the vertical opening, and forming a transistor having a channel region extending along a vertical portion of the step, the vertical surface lying outside of and being laterally displaced from the vertical opening, the transistor being electrically connected to the storage capacitor by an outdiffusion of the conductive strap.
The forming of the conductive strap includes removing an upper portion of an insulator surrounding the storage capacitor to form a strap gap and filling the strap gap with a conductive material. The forming of the transistor includes lithographically forming a gate opening in the substrate over the storage capacitor, the gate opening having at least one wall laterally displaced from the vertical opening, wherein the wall of the gate opening includes the vertical surface. The forming of the transistor further includes forming first spacers in the gate opening, and forming a strap opening in the substrate using the first spacers to align the strap opening and wherein the conductive strap is formed by forming second spacers in the strap opening. This process also includes removing the first spacers and a portion of the second spacers to form the step, the outdiffusion being formed in a portion of the step adjacent the second spacers.
The gate opening is wider than the strap opening, thereby forming the step. The manufacturing of the integrated circuit chip further includes forming a gate conductor adjacent the vertical surface, wherein a voltage in the gate conductor makes the channel region conductive, electrically connecting the transistor and the storage capacitor via the conductive strap and the outdiffusion.
An integrated circuit chip according to the invention includes a storage capacitor located in a vertical opening in a horizontal substrate, a transistor having a channel region extending along a vertical surface, the vertical surface lying outside of and being laterally displaced from the vertical opening, and a conductive strap laterally extending from the vertical opening, the conductive strap having an outdiffusion electrically connecting the transistor to the storage capacitor.
The integrated circuit chip further includes an insulator surrounding the storage capacitor and a strap gap in an upper portion of the insulator, the conductive strap being located in the strap gap. The vertical transistor includes a gate opening in the substrate over the storage capacitor, the gate opening having at least one wall laterally displaced from the vertical opening, wherein the wall of the gate opening includes the vertical surface. The integrated circuit chip further includes a strap opening in the substrate aligned with first spacers in the gate opening and second spacers in the strap opening, wherein a portion of the second spacers comprise the conductive strap. The invention further includes a step formed by a width difference in the gate opening and the strap opening, the outdiffusion being located in a portion of the step adjacent the conductive strap. The integrated circuit chip also includes a gate conductor adjacent the vertical surface, wherein a voltage in the gate conductor makes the channel region conductive, electrically connecting the transistor and the storage capacitor via the conductive strap and the outdiffusion.
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Gruening Ulrike
Radens Carl J.
International Business Machines - Corporation
McGinn & Gibb PLLC
Neff, Esq Daryl K.
Wojciechowicz Edward
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