Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-31
2001-08-21
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S384000, C257S754000
Reexamination Certificate
active
06278163
ABSTRACT:
TECHNICAL FIELD
This invention relates to an HV (High Voltage) transistor and corresponding manufacturing process, in particular in processes employing silicides.
More particularly, but not exclusively, the invention relates to an HV transistor for integration in the same substrate as other devices intended for operation on relatively high voltages, e.g., non-volatile memories of the EEPROM and Flash-EEPROM types, and devices which are to operate at high speeds, and the description that follows will cover this field of application for convenience of explanation.
BACKGROUND OF THE INVENTION
As is well known, to improve the speed of devices, the current technology for manufacturing semiconductor integrated circuits has succeeded in greatly reducing the resistance of interconnects and contacts of the individual devices, through the use of composite materials comprising silicon and a transition metal such as titanium or tungsten. These composite materials are termed silicides and used for forming layers with relatively low resistivity.
In particular, the formation of a silicide layer over the active areas of a MOS transistor comprises the following steps, subsequent to forming the transistor gate:
implanting first portions of the source and drain regions with dopant at a low concentration;
forming spacers adjacent to the gate and interconnect lines;
implanting second portions, comprised in the source and drain regions of the transistor, at a high concentration;
depositing a transition metal over the entire surface of the substrate;
applying a thermal process, whereby the transition metal reacts selectively with the substrate surface to yield silicide in areas not covered with dielectric.
By these process steps, the silicide deposition can be extended to also cover the polysilicon which constitutes the gates and interconnects of the transistor, since the etching steps for clearing the active areas of the oxide which overlies them have a similar effect on the interconnects formed of polysilicon lines.
However, silicide layers cannot be used in the fabrication of high voltage devices, especially HV (High Voltage) transistors of either the P-channel or the N-channel type formed by a DE (Drain Extension) technique. In these devices, the source and drain diffusions are lightly doped regions, so as to provide HV transistors with a sufficiently high breakdown voltage for operation on high bias and working voltages.
The process for producing silicide layers may develop problems on account of the light dopant concentration and small thickness of such regions. For example, during the thermal process for reacting the transition metal layer with the substrate surface, a surface layer of substrate is expended, and some dopant is taken up from the substrate by the silicide layer. Thus, in normal operation of the device, the silicide layer is shorted to the substrate.
Another problem with these high voltage transistors comes from the high strength electric fields which are created between the border of the active area of the transistor and the field oxide.
In addition, these high voltage transistors are often integrated in the same substrate as low voltage transistors. The low voltage transistors should have a short channel and have source and drain regions formed by implantations at a sufficient energy and dopant concentration to ensure retention of the source and drain regions after the formation of the silicide layer required to provide adequately fast performance of the low voltage transistors.
However, it is undesirable to increase the number of the implantations and masks used for differentiating the high voltage transistors from the low voltages ones.
SUMMARY OF THE INVENTION
An embodiment of this invention provides a high voltage transistor with such structural features as to prevent the onset of strong electric fields in the silicon border region between the field oxide and the active area of the transistor containing the source and drain regions.
Furthermore, it is an object of this invention to provide a process whereby the number of steps for simultaneously forming high and low voltage transistors can be minimized.
Specifically, the embodiment is directed to an HV transistor integrated in a semiconductor substrate having a first type of conductivity, which transistor has a gate region included between corresponding drain and source regions, with at least said drain region being lightly doped with a second type of conductivity.
The invention also relates to a process for manufacturing an HV transistor having a gate region included between corresponding drain and source regions, which process comprises a first step of implanting a first type of dopant at a low dopant concentration to form at least the drain region.
The embodiment further provides a high voltage transistor with contact pads effective to establish a direct contact with the source and drain regions.
A transistor according to the invention affords improved integration of high voltage transistors with devices formed of silicide layers, such as low voltage transistors.
A transistor according to the invention also allows the contact resistances to be reduced.
The features and advantages of the device according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 5683924 (1997-11-01), Chan et al.
patent: 5844274 (1998-12-01), Tsutsumi
patent: 5914518 (1999-06-01), Nguyen et al.
patent: 5945710 (1999-08-01), Oda et al.
patent: 5945738 (1999-08-01), Nguyen et al.
patent: 5949105 (1999-09-01), Moslehi
patent: 0747941A2 (1996-12-01), None
patent: 60117674 (1985-06-01), None
patent: 01094666 (1989-04-01), None
Pio Federico
Riva Carlo
Chaudhuri Olik
Galanthay Theodore E.
Iannucci Robert
Peralta Ginette
Seed IP Law Group PLLC
LandOfFree
HV transistor structure and corresponding manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with HV transistor structure and corresponding manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and HV transistor structure and corresponding manufacturing method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2475648