Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-01-29
2000-03-28
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 57, 714763, 714723, G06F 1100
Patent
active
060444797
ABSTRACT:
A method and apparatus are described for providing a human sensorially significant indication of the occurrence of a sequence of error events in an ECC system as they occur over time. Each error indication element is kept activated for a human sensorially significant ("HSS") time interval which is tracked by maintaining a count of refresh pulses received from a memory system. A HSS interval timer includes a D-type flip flop which pulses a binary counter for each refresh operation. The counter, when full, produces a reset signal. An error indication signal from an ECC system is provided to a error condition latch which activates a sensorial error indicator element if the error indication signal is provided to the latch while the memory system is performing a memory read operation. The latch is subsequently reset by the reset signal from the counter after a HSS interval has transpired. Further embodiments provide separate HSS indications for single and multiple bit errors as well as a static indication of the detection of an uncorrectable error.
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Beausoliel, Jr. Robert W.
Ehrlich Marc A.
International Business Machines - Corporation
Kormanyos Peter
LandOfFree
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