Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-11-23
2003-05-06
Rinehart, Mark H. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S310000
Reexamination Certificate
active
06560666
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to chipset technologies generally and particularly to impedance compensation techniques.
BACKGROUND OF THE INVENTION
As integrated circuit technologies continue to advance, the frequencies at which the integrated circuits operate increase accordingly. Circuit designers often have difficulties in continuously increasing bus speeds, because input/output (hereinafter I/O) buffers connected to the buses often operate across a wide variety of operation conditions. Specifically, the performance of a buffer changes significantly over process, voltage and temperature variations. As these conditions change, the noise and response characteristics of the buffers are also affected. For stable operation, circuit designers often limit the speed at which the buffer circuits such as I/O buffers operate to accommodate the potential variations in conditions.
Alternatively, impedance compensation provides a mechanism to maintain the optimum characteristics of an I/O buffer over a wide range of operating conditions. Impedance compensation varies the output impedance of the I/O buffer to match the line impedance of a line connected to the I/O buffer. As a result, signal reflections and inter-symbol interference on the line are reduced or eliminated. This preservation of signal integrity also allows higher speed of transmission. Moreover, impedance compensation allows integrated circuit manufacturers to make on-die termination devices, which not only saves cost, but also improves reliability.
Interfaces among components in a computer system are commonly used to further improve the overall performance of the system. For the reasons detailed above, performing impedance compensation update on signals of these interfaces is often necessary to meet specified timing requirements. Traditionally, each signal on the interfaces is updated with some impedance compensation adjustment value independently to prevent glitches on the signal. As more interfaces exist and more signals travel on these interfaces, the designs for the update logic to update the signals and for the validation unit to ensure the signals to be glitch-free become complicated and, thus, costly.
Therefore, in order to simplify the designs mentioned above, a method and apparatus is needed to place interfaces in a known state, where all the signals on the interfaces can be updated at once while still maintaining the integrity of the signals.
SUMMARY OF THE INVENTION
A method and apparatus of performing impedance compensation on signals on interfaces between chipset components is disclosed.
In one embodiment, a present impedance adjustment value is generated, and a controlled impedance adjustment value is also established based on the present impedance adjustment value. Then a special cycle with a deterministic amount of time is generated to stabilize the interfaces. With the interfaces in a known state, the signals on the interfaces are updated with the controlled impedance adjustment value during the special cycle, and the signals are ensured to be glitch-free.
REFERENCES:
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patent: 5696768 (1997-12-01), Harriman et al.
patent: 6097219 (2000-08-01), Urata et al.
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patent: 6212583 (2001-04-01), Shimura
Harriman David J.
Volk Andrew M.
Phan Raymond N
Rinehart Mark H.
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