Hub chip for one or more memory modules

Details Hub chip for one or more memory modules Hub chip for one or more memory modules

2007-03-13

2007-03-13

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S305000, C710S100000

Reexamination Certificate

active

10877139

ABSTRACT:
One embodiment of the invention provides a hub chip comprising: an address bus input for receiving a plurality of successively sent portions of address and/or command data, a shift register which has register elements and is connected to the address bus input to receive the plurality of portions of the address and/or command data, the shift register being connected to the address bus input so that, when the address and/or command data are received, the portions of the address and/or command data are successively written to the register elements, an address bus output for outputting the received address and/or command data, a memory module interface for connecting one or more memory modules, where the hub chip addresses none, one or a plurality of the connected memory modules, depending on the address and/or command data transferred, and a driver element provided to output the received portion of the address and/or command data to the address bus output before all of the portions of the address and/or command data have been received in full.

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German Patent Office Examination Report dated Apr. 29, 2004.
German Patent Office Examination Report dated Jul. 28, 2005.
German Examination Report Dated Apr. 29, 2004.
German Patent Office Examination Report dated Nov. 9, 2005.

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