Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-27
2003-12-30
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C257S356000, C257S357000
Reexamination Certificate
active
06670676
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing electrostatic discharge (ESD) devices generally and, more particularly, to a hot socketable, soft pull circuit for ESD devices.
BACKGROUND OF THE INVENTION
Networks, telecommunication systems and other mission critical applications cannot tolerate circuit downtime. In particular, circuit boards for networks and telecommunication systems need to be capable of being replaced within operational systems. Insertion of a circuit board in an operational circuit may result in voltages being applied to signal input/output pins before voltage is applied to the power supply pins. Hot socketability refers to the removal and/or insertion of components or circuit boards within a system while the system is running. Programmable Logic Device (PLD) circuits are used in many networking and telecommunications systems. Hot socketability is a desirable function on PLD products. In addition, more dense integrated circuits are increasingly more susceptible to ESD damage as the oxide layers become thinner. With integrated circuit technology developing continuously more dense circuits, ESD performance, in general, is degrading. As a result of more dense circuitry, soft pull circuitry is required. Soft pull circuits on ESD devices need to meet the hot socketability requirement.
Referring to
FIG. 1
, a schematic diagram of a circuit
10
illustrating a conventional ESD device circuit is shown. The circuit
10
includes a soft pull circuit
12
. The soft pull circuit
12
is powered with either a supply voltage VCC or a PAD voltage, whichever becomes active first. Since the ESD device can conduct when VCC is not active, the circuit
10
is not hot socketable. However, the conductivity of the circuit
10
can depend on the voltage of the device and the voltage level of VCC and PAD.
Referring to
FIG. 2
, a schematic diagram of a circuit
20
illustrating a convention power supply clamp is shown. The power supply clamp
20
is configured to control a voltage level of the voltage VCC
1
. The power supply clamp
20
includes a transistor
22
, a transistor
24
and a resistor
26
. The voltage VCC
1
is coupled to an emitter of the transistor
22
and the voltage VCC
2
is coupled to a collector of the transistor
22
. The transistor
22
is controlled by the transistor
24
. The voltage VCC
2
is configured to control the transistor
24
via the resistor
26
. The power supply clamp
20
is designed specifically for a particular voltage tolerance and has limited applicability.
In general, ESD device circuits (such as the circuit
10
or the circuit
20
) that use a single soft pull circuit between the ESD device and ground when there are multiple voltage inputs and VCC are not hot socketable. Any of the input voltages (i.e., VCCS) to the soft pull circuit
12
may vary between 0V and a regular value. If the input voltage to the soft pull circuit
12
is not active, the soft pull circuit
12
turns off. Turning off the soft pull circuit
12
causes the ESD device circuit
10
to turn on in violation of the hot socketability requirement.
It would be desirable to (i) ensure the ESD device will be effectively grounded when any VCC (or multiple VCCS) or PAD becomes active, (ii) ensure the soft pull function turns on at the same threshold voltage as the ESD device, (iii) incorporate a simple circuit to minimize circuit board space, and (iv) provide circuit ESD protection at transient voltages above 5000V.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit. The first circuit may be configured to limit conduction between a first and a second power supply pin in response to one or more control signals. One or more of a plurality of paths may limit the conduction in response to one or more voltages.
The objects, features and advantages of the present invention include providing a method and/or architecture that may provide (i) multiple soft pull circuits that effectively ground an ESD device when a voltage (e.g., relevant supply voltages VCCs or PAD) becomes active and/or (ii) a soft pull circuit that simultaneously turns on with an ESD device.
REFERENCES:
patent: 6134517 (2000-10-01), Baxter et al.
patent: 6175952 (2001-01-01), Patel et al.
patent: 6226779 (2001-05-01), Baxter et al.
patent: 406232349 (1994-08-01), None
A 4.9ns, 3.3 Volt, 512 Macrocell, CMOS PLD with Hot Socket Protection and Fast In System Programming, By Brad Vest et al., IEEE 1999 Custom Integrated Circuits Conference, pp. 187-190.
Chaudhuri Olik
Cypress Semiconductor Corp.
Ha Nathan W.
Maiorana P.C. Christopher P.
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